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2026-02-09 - 19:03
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack2slot6.osadl.org (updated Mon Feb 09, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18682995711cyclictest28095-21munin-node10:30:000
18682995015cyclictest30656-21kworker/0:208:09:220
18682994917cyclictest30656-21kworker/0:208:48:580
18682994827cyclictest0-21swapper09:55:250
18682994815cyclictest30656-21kworker/0:210:48:110
18682994814cyclictest30656-21kworker/0:209:17:340
18682994814cyclictest30656-21kworker/0:208:13:370
18682994730cyclictest0-21swapper09:32:310
18682994728cyclictest0-21swapper10:52:170
18682994716cyclictest30656-21kworker/0:209:45:500
18682994713cyclictest30656-21kworker/0:208:37:310
18682994625cyclictest0-21swapper10:14:520
18682994616cyclictest30656-21kworker/0:211:00:200
18682994616cyclictest30656-21kworker/0:208:14:590
18682994615cyclictest30656-21kworker/0:210:36:510
18682994615cyclictest30656-21kworker/0:210:19:450
18682994615cyclictest30656-21kworker/0:209:04:120
18682994615cyclictest30656-21kworker/0:208:52:490
18682994615cyclictest30656-21kworker/0:207:40:410
18682994614cyclictest30656-21kworker/0:208:22:500
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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