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2022-01-26 - 11:53

Intel(R) Celeron(R) M processor 1.50GHz, Linux 3.2.39-rt59 (Profile)

Latency plot of system in rack #2, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack2slot6.osadl.org (updated Wed Jan 26, 2022 00:43:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31444996323cyclictest0-21swapper22:28:520
31444996127cyclictest0-21swapper22:39:130
31444996127cyclictest0-21swapper22:16:230
31444996126cyclictest0-21swapper23:36:190
31444996125cyclictest0-21swapper23:21:590
31444996028cyclictest0-21swapper22:45:280
31444996028cyclictest0-21swapper22:14:380
31444996027cyclictest0-21swapper23:35:260
31444996026cyclictest0-21swapper22:32:220
31444996026cyclictest0-21swapper22:00:570
31444996026cyclictest0-21swapper00:01:420
31444996024cyclictest0-21swapper23:27:110
31444996022cyclictest0-21swapper23:59:260
31444995927cyclictest0-21swapper21:47:140
31444995927cyclictest0-21swapper21:32:340
31444995926cyclictest0-21swapper00:25:060
31444995925cyclictest0-21swapper23:48:460
31444995923cyclictest0-21swapper00:43:240
31444995827cyclictest0-21swapper21:45:060
31444995825cyclictest0-21swapper00:30:070
31444995824cyclictest0-21swapper23:07:090
31444995824cyclictest0-21swapper00:36:260
31444995727cyclictest0-21swapper23:41:590
31444995725cyclictest0-21swapper23:16:010
31444995725cyclictest0-21swapper22:53:020
31444995725cyclictest0-21swapper22:11:110
31444995724cyclictest0-21swapper00:32:120
31444995723cyclictest0-21swapper22:59:060
31444995625cyclictest0-21swapper00:21:020
31444995623cyclictest0-21swapper23:17:030
31444995623cyclictest0-21swapper23:03:580
31444995623cyclictest0-21swapper21:53:220
31444995623cyclictest0-21swapper01:00:550
31444995522cyclictest0-21swapper00:55:260
31444995429cyclictest0-21swapper00:47:220
31444995428cyclictest0-21swapper23:54:490
31444995427cyclictest0-21swapper22:49:150
31444995425cyclictest0-21swapper22:01:460
31444995420cyclictest0-21swapper22:23:580
31444995329cyclictest0-21swapper00:15:350
31444995327cyclictest0-21swapper00:09:530
31444995221cyclictest0-21swapper21:37:270
31444993611cyclictest447-21munin-node21:01:420
31444993525cyclictest10787-21ls21:31:160
31444993410cyclictest0-21swapper19:53:330
3144499339cyclictest4705-21munin-node19:46:420
3144499339cyclictest0-21swapper20:26:470
3144499339cyclictest0-21swapper20:26:140
31444993322cyclictest8936-21ntpdc19:56:470
31444993322cyclictest1191-21crond20:13:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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