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2026-01-25 - 10:16
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 792 highest latencies:
System rack2slot6.osadl.org (updated Sun Jan 25, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31338995632cyclictest8734-21kworker/0:021:30:170
31338995426cyclictest0-21swapper20:34:350
31338995327cyclictest0-21swapper21:25:170
31338995325cyclictest0-21swapper22:06:570
31338995227cyclictest0-21swapper23:14:250
31338995226cyclictest0-21swapper21:19:520
31338995225cyclictest8734-21kworker/0:020:58:320
31338995024cyclictest0-21swapper23:02:050
31338994927cyclictest0-21swapper22:47:170
31338994915cyclictest8734-21kworker/0:021:09:350
31338994825cyclictest0-21swapper20:11:210
31338994824cyclictest0-21swapper23:05:460
31338994820cyclictest0-21swapper22:01:500
31338994815cyclictest8734-21kworker/0:022:31:590
31338994814cyclictest8734-21kworker/0:022:55:260
31338994726cyclictest0-21swapper23:26:280
31338994723cyclictest0-21swapper21:11:110
31338994715cyclictest8734-21kworker/0:021:50:450
31338994714cyclictest8734-21kworker/0:021:19:260
31338994713cyclictest28369-21kworker/0:220:00:400
31338994713cyclictest0-21swapper21:37:300
31338994626cyclictest0-21swapper21:47:440
31338994625cyclictest0-21swapper22:15:050
31338994620cyclictest0-21swapper23:23:530
31338994615cyclictest8734-21kworker/0:021:55:310
31338994615cyclictest8734-21kworker/0:020:49:500
31338994614cyclictest8734-21kworker/0:020:36:370
31338994613cyclictest28369-21kworker/0:220:16:590
31338994528cyclictest0-21swapper20:05:090
31338994526cyclictest0-21swapper20:41:020
31338994525cyclictest0-21swapper22:50:590
31338994520cyclictest0-21swapper22:10:460
31338994518cyclictest0-21swapper21:41:310
31338994515cyclictest8734-21kworker/0:021:04:220
31338994514cyclictest8734-21kworker/0:022:35:430
31338994514cyclictest28369-21kworker/0:220:26:570
31338994513cyclictest8734-21kworker/0:022:26:510
31338994419cyclictest0-21swapper22:19:550
31338994416cyclictest28369-21kworker/0:220:22:270
31338994415cyclictest8734-21kworker/0:022:40:240
31338994415cyclictest8734-21kworker/0:020:53:290
31338994310cyclictest0-21swapper23:15:140
3133899349cyclictest10782-21munin-node18:30:190
31338993413cyclictest0-21swapper18:03:280
31338993411cyclictest0-21swapper18:45:260
3133899339cyclictest0-21swapper18:15:410
31338993311cyclictest0-21swapper19:00:190
31338993310cyclictest899-21munin-node18:05:200
31338993310cyclictest0-21swapper18:23:270
3133899329cyclictest0-21swapper19:55:350
3133899329cyclictest0-21swapper19:42:370
3133899329cyclictest0-21swapper19:24:340
3133899329cyclictest0-21swapper18:51:010
3133899328cyclictest0-21swapper18:35:540
31338993213cyclictest0-21swapper19:45:540
31338993212cyclictest0-21swapper18:56:370
31338993210cyclictest0-21swapper19:36:310
3133899319cyclictest0-21swapper19:50:320
31338993122cyclictest0-21swapper18:25:130
31338993121cyclictest37292sleep018:10:230
31338993121cyclictest0-21swapper19:05:210
31338993120cyclictest26484-21munin-node19:10:100
31338993118cyclictest0-21swapper19:25:000
31338993110cyclictest0-21swapper19:15:200
31338993110cyclictest0-21swapper18:42:180
31338993019cyclictest2065-21cpuspeed19:30:090
2969722311sleep029860-21if_eth117:55:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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