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2023-05-31 - 18:17

x86 AMD A10 7850K Kaveri @3700 MHz, Linux 4.18.7-rt5 (Profile)

Latency plot of system in rack #2, slot #7
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack2slot7.osadl.org (updated Wed Mar 10, 2021 12:43:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
165732122111,0sleep10-21swapper/107:19:141
164422116105,0sleep20-21swapper/207:17:312
164132116100,0sleep00-21swapper/007:17:090
157332116104,0sleep30-21swapper/307:17:003
17055995549,0cyclictest0-21swapper/007:21:500
1705899240,0cyclictest9821-21ls11:52:033
1705799240,0cyclictest6104-21python11:47:012
1705799240,0cyclictest1820-21nscd11:35:512
1705599240,0cyclictest24668-21ssh12:12:150
121220,0rcu_sched0-21swapper/312:36:583
17055992015,0cyclictest4795-21snmpd08:54:590
17055991916,0cyclictest101ktimersoftd/011:02:020
17055991916,0cyclictest101ktimersoftd/009:50:360
17055991914,0cyclictest4795-21snmpd08:41:380
1705599191,0cyclictest0-21swapper/009:44:000
111190,0rcu_preempt0-21swapper/008:31:500
17058991818,0cyclictest431ktimersoftd/310:39:413
17055991818,0cyclictest101ktimersoftd/012:25:010
17055991815,0cyclictest101ktimersoftd/010:03:510
111180,0rcu_preempt44-21ksoftirqd/308:31:503
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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