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2021-04-12 - 08:47

Intel(R) Core(TM)2 Quad CPU @ 2.40GHz, Linux 3.2.46-rt67-32 (Profile)

Latency plot of system in rack #3, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100, highest latencies:
System rack3slot1.osadl.org (updated Mon Apr 12, 2021 00:43:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2632999135123cyclictest0-21swapper/116:37:521
2632999104102cyclictest30421-21tune2fs18:02:491
2632999104102cyclictest13484-21tune2fs17:22:501
2633099103102cyclictest0-21swapper/218:32:482
2633099103102cyclictest0-21swapper/217:22:502
2633099103102cyclictest0-21swapper/216:37:522
26330999392cyclictest0-21swapper/218:02:492
26330999392cyclictest0-21swapper/216:27:572
26330998685cyclictest0-21swapper/216:12:542
26329998682cyclictest0-21swapper/120:32:381
26329998583cyclictest18063-21tune2fs16:17:521
26330998482cyclictest0-21swapper/216:17:522
26330998472cyclictest0-21swapper/219:37:482
26329998473cyclictest15545-21tune2fs17:27:501
26329998472cyclictest0-21swapper/119:12:411
26330998382cyclictest0-21swapper/220:37:472
26330998382cyclictest0-21swapper/220:32:512
26330998382cyclictest0-21swapper/220:32:382
26330998382cyclictest0-21swapper/220:17:562
26330998382cyclictest0-21swapper/220:12:522
26330998382cyclictest0-21swapper/220:02:532
26330998382cyclictest0-21swapper/219:57:452
26330998382cyclictest0-21swapper/219:22:402
26330998382cyclictest0-21swapper/219:07:462
26330998382cyclictest0-21swapper/218:52:582
26330998382cyclictest0-21swapper/218:52:582
26330998382cyclictest0-21swapper/218:47:462
26330998382cyclictest0-21swapper/218:23:022
26330998382cyclictest0-21swapper/217:57:502
26330998382cyclictest0-21swapper/217:32:582
26330998382cyclictest0-21swapper/216:48:012
26330998382cyclictest0-21swapper/216:47:472
26330998382cyclictest0-21swapper/216:32:522
26330998382cyclictest0-21swapper/216:23:012
26330998382cyclictest0-21swapper/216:07:482
26330998382cyclictest0-21swapper/215:57:582
26330998382cyclictest0-21swapper/215:53:592
26330998382cyclictest0-21swapper/215:38:072
26330998382cyclictest0-21swapper/215:27:552
26330998361cyclictest0-21swapper/219:36:382
26329998382cyclictest0-21swapper/120:37:471
26329998382cyclictest0-21swapper/120:32:511
26329998382cyclictest0-21swapper/120:17:561
26329998382cyclictest0-21swapper/120:12:521
26329998382cyclictest0-21swapper/120:02:531
26329998382cyclictest0-21swapper/119:57:451
26329998382cyclictest0-21swapper/119:42:401
26329998382cyclictest0-21swapper/119:22:401
26329998382cyclictest0-21swapper/118:52:551
26329998382cyclictest0-21swapper/118:52:551
26329998382cyclictest0-21swapper/118:47:461
26329998382cyclictest0-21swapper/118:32:431
26329998382cyclictest0-21swapper/118:23:021
26329998382cyclictest0-21swapper/117:57:501
26329998382cyclictest0-21swapper/117:32:581
26329998382cyclictest0-21swapper/116:53:011
26329998382cyclictest0-21swapper/116:48:011
26329998382cyclictest0-21swapper/116:47:471
26329998382cyclictest0-21swapper/116:32:521
26329998382cyclictest0-21swapper/116:32:471
26329998382cyclictest0-21swapper/116:23:011
26329998382cyclictest0-21swapper/116:07:421
26329998382cyclictest0-21swapper/115:57:581
26329998382cyclictest0-21swapper/115:53:591
26329998382cyclictest0-21swapper/115:38:071
26329998382cyclictest0-21swapper/115:22:591
26329998381cyclictest4477-21tune2fs18:17:491
26329998381cyclictest10955-21tune2fs18:32:481
26330998281cyclictest0-21swapper/220:47:422
26330998281cyclictest0-21swapper/220:42:462
26330998281cyclictest0-21swapper/220:07:452
26330998281cyclictest0-21swapper/218:17:492
26330998281cyclictest0-21swapper/216:52:512
26330998281cyclictest0-21swapper/215:22:552
26330997675cyclictest0-21swapper/218:07:482
26330997372cyclictest0-21swapper/219:52:432
26330997372cyclictest0-21swapper/219:42:432
26330997372cyclictest0-21swapper/219:12:542
26330997372cyclictest0-21swapper/217:47:462
26330997372cyclictest0-21swapper/217:37:552
26330997372cyclictest0-21swapper/217:12:482
26330997372cyclictest0-21swapper/215:33:042
26330997351cyclictest0-21swapper/219:23:402
26329997372cyclictest0-21swapper/120:47:401
26329997372cyclictest0-21swapper/120:44:091
26329997372cyclictest0-21swapper/120:22:421
26329997372cyclictest0-21swapper/120:22:421
26329997372cyclictest0-21swapper/120:07:461
26329997372cyclictest0-21swapper/119:53:371
26329997372cyclictest0-21swapper/119:52:401
26329997372cyclictest0-21swapper/119:26:071
26329997372cyclictest0-21swapper/119:12:411
26329997372cyclictest0-21swapper/118:59:431
26329997372cyclictest0-21swapper/118:44:131
26329997372cyclictest0-21swapper/118:37:471
26329997372cyclictest0-21swapper/117:42:521
26329997372cyclictest0-21swapper/117:37:531
26329997372cyclictest0-21swapper/117:07:481
26329997372cyclictest0-21swapper/116:57:511
26329997372cyclictest0-21swapper/116:17:481
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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