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2023-01-27 - 16:40

x86 Intel Core2 Quad @2400 MHz, Linux 3.2.46-rt67-32 (Profile)

Latency plot of system in rack #3, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100, Linux 4.9.20-rt16, x86_64 highest latencies:
System rack3slot1.osadl.org (updated Fri Jan 27, 2023 12:43:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
254389911092cyclictest0-21swapper/303:35:493
254389910892cyclictest0-21swapper/301:50:423
2543899108103cyclictest0-21swapper/304:05:423
2543899108103cyclictest0-21swapper/303:50:183
254389910792cyclictest0-21swapper/305:50:383
254389910792cyclictest0-21swapper/303:25:433
2543899107103cyclictest0-21swapper/302:10:443
254389910692cyclictest0-21swapper/303:13:423
2542799104102cyclictest32459-21tune2fs01:55:392
25438999992cyclictest32729-21tune2fs07:00:243
25438999692cyclictest0-21swapper/301:40:233
25438999392cyclictest0-21swapper/305:25:333
25438998982cyclictest3761-21latency_hist02:05:223
25438998972cyclictest0-21swapper/307:05:343
25438998972cyclictest0-21swapper/305:35:373
25438998972cyclictest0-21swapper/305:20:353
25438998972cyclictest0-21swapper/304:30:443
25438998972cyclictest0-21swapper/304:00:373
25438998872cyclictest0-21swapper/306:55:253
25438998872cyclictest0-21swapper/306:45:313
25438998872cyclictest0-21swapper/306:30:363
25438998872cyclictest0-21swapper/306:30:363
25438998872cyclictest0-21swapper/306:25:283
25438998872cyclictest0-21swapper/306:20:273
25438998872cyclictest0-21swapper/306:15:243
25438998872cyclictest0-21swapper/306:05:293
25438998872cyclictest0-21swapper/306:00:133
25438998872cyclictest0-21swapper/305:55:283
25438998872cyclictest0-21swapper/305:40:323
25438998872cyclictest0-21swapper/305:15:343
25438998872cyclictest0-21swapper/305:00:413
25438998872cyclictest0-21swapper/304:57:463
25438998872cyclictest0-21swapper/304:50:433
25438998872cyclictest0-21swapper/304:48:203
25438998872cyclictest0-21swapper/304:40:333
25438998872cyclictest0-21swapper/304:35:383
25438998872cyclictest0-21swapper/304:20:353
25438998872cyclictest0-21swapper/304:10:343
25438998872cyclictest0-21swapper/303:55:343
25438998872cyclictest0-21swapper/303:20:343
25438998872cyclictest0-21swapper/303:15:343
25438998872cyclictest0-21swapper/303:05:413
25438998872cyclictest0-21swapper/303:05:193
25438998872cyclictest0-21swapper/302:51:073
25438998872cyclictest0-21swapper/302:45:373
25438998872cyclictest0-21swapper/302:40:443
25438998872cyclictest0-21swapper/302:25:363
25438998872cyclictest0-21swapper/302:20:453
25438998872cyclictest0-21swapper/302:20:213
25438998872cyclictest0-21swapper/302:05:413
25438998772cyclictest0-21swapper/306:50:383
25438998772cyclictest0-21swapper/306:40:373
25438998772cyclictest0-21swapper/306:10:323
25438998772cyclictest0-21swapper/305:30:423
25438998772cyclictest0-21swapper/305:05:393
25438998772cyclictest0-21swapper/304:15:333
25438998772cyclictest0-21swapper/303:50:353
25438998772cyclictest0-21swapper/303:30:463
25438998772cyclictest0-21swapper/302:55:453
25438998772cyclictest0-21swapper/302:55:453
25438998772cyclictest0-21swapper/302:35:453
25438998772cyclictest0-21swapper/302:30:373
25438998772cyclictest0-21swapper/301:55:363
25438998772cyclictest0-21swapper/301:45:233
25438998772cyclictest0-21swapper/301:40:473
25427998782cyclictest11701-21tune2fs06:10:322
25427998782cyclictest0-21swapper/202:05:432
25438998672cyclictest0-21swapper/305:45:373
25438998672cyclictest0-21swapper/305:10:403
25438998672cyclictest0-21swapper/303:43:373
25427998572cyclictest13815-21tune2fs06:15:262
25427998482cyclictest10389-21tune2fs03:35:382
25427998472cyclictest18623-21gltestperf05:10:342
25438998382cyclictest32677-21runrttasks04:25:593
25427998382cyclictest0-21swapper/207:05:342
25427998382cyclictest0-21swapper/206:55:352
25427998382cyclictest0-21swapper/206:45:362
25427998382cyclictest0-21swapper/206:30:262
25427998382cyclictest0-21swapper/206:30:262
25427998382cyclictest0-21swapper/206:25:372
25427998382cyclictest0-21swapper/206:20:422
25427998382cyclictest0-21swapper/206:05:382
25427998382cyclictest0-21swapper/206:04:092
25427998382cyclictest0-21swapper/205:55:432
25427998382cyclictest0-21swapper/205:40:332
25427998382cyclictest0-21swapper/205:35:482
25427998382cyclictest0-21swapper/205:25:432
25427998382cyclictest0-21swapper/205:20:452
25427998382cyclictest0-21swapper/205:00:442
25427998382cyclictest0-21swapper/204:55:562
25427998382cyclictest0-21swapper/204:53:582
25427998382cyclictest0-21swapper/204:45:412
25427998382cyclictest0-21swapper/204:40:332
25427998382cyclictest0-21swapper/204:35:442
25427998382cyclictest0-21swapper/204:20:432
25427998382cyclictest0-21swapper/204:05:462
25427998382cyclictest0-21swapper/204:03:502
25427998382cyclictest0-21swapper/203:55:422
25427998382cyclictest0-21swapper/203:50:442
25427998382cyclictest0-21swapper/203:45:532
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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