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2023-02-04 - 23:58

x86 Intel Core2 Quad @2400 MHz, Linux 3.2.46-rt67-32 (Profile)

Latency plot of system in rack #3, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100, highest latencies:
System rack3slot1.osadl.org (updated Sat Feb 04, 2023 12:43:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2224499110102cyclictest30453-21tune2fs04:23:162
2224599105103cyclictest0-21swapper/301:33:083
2224499104102cyclictest27346-21tune2fs06:48:122
2224599103102cyclictest0-21swapper/306:38:243
2224599103102cyclictest0-21swapper/306:03:123
2224599103102cyclictest0-21swapper/301:43:303
2224499103102cyclictest26949-21tune2fs01:43:302
2224499103102cyclictest0-21swapper/206:38:242
2224499103102cyclictest0-21swapper/202:33:252
2224499103102cyclictest0-21swapper/202:33:252
22244999492cyclictest31147-21tune2fs01:53:222
22244999492cyclictest15010-21tune2fs05:03:142
22244998982cyclictest32142-21tune2fs05:43:142
22244998982cyclictest24157-21tune2fs04:08:302
22244998882cyclictest0-21swapper/206:07:582
22244998882cyclictest0-21swapper/202:43:212
22244998782cyclictest0-21swapper/206:07:582
22244998782cyclictest0-21swapper/205:58:222
22244998782cyclictest0-21swapper/205:18:232
22244998782cyclictest0-21swapper/204:18:272
22244998782cyclictest0-21swapper/203:23:042
22244998782cyclictest0-21swapper/203:08:262
22244998782cyclictest0-21swapper/202:41:072
22244998682cyclictest0-21swapper/207:01:432
22244998682cyclictest0-21swapper/206:56:432
22244998682cyclictest0-21swapper/206:46:412
22244998682cyclictest0-21swapper/206:31:392
22244998682cyclictest0-21swapper/203:53:262
22244998682cyclictest0-21swapper/202:58:292
22244998682cyclictest0-21swapper/202:56:082
22244998682cyclictest0-21swapper/202:48:372
22244998682cyclictest0-21swapper/202:03:302
22244998682cyclictest0-21swapper/201:48:392
22244998671cyclictest0-21swapper/206:22:572
22245998583cyclictest0-21swapper/304:08:253
22245998583cyclictest0-21swapper/302:18:193
22244998583cyclictest13824-21fschecks_time02:28:222
22245998483cyclictest0-21swapper/306:15:113
22245998482cyclictest28649-21fschecks_count03:03:203
22244998482cyclictest23465-21tune2fs05:23:142
22244998482cyclictest15682-21tune2fs03:48:412
22244998482cyclictest15682-21tune2fs03:48:412
22244998482cyclictest11569-21tune2fs02:23:212
22245998382cyclictest31282-21grep01:53:223
22245998382cyclictest0-21swapper/306:18:223
22245998382cyclictest0-21swapper/305:56:333
22245998382cyclictest0-21swapper/305:38:233
22245998382cyclictest0-21swapper/305:27:143
22245998382cyclictest0-21swapper/305:21:283
22245998382cyclictest0-21swapper/304:58:193
22245998382cyclictest0-21swapper/304:13:253
22245998382cyclictest0-21swapper/304:03:023
22245998382cyclictest0-21swapper/303:33:263
22245998382cyclictest0-21swapper/303:28:253
22245998382cyclictest0-21swapper/303:23:223
22245998382cyclictest0-21swapper/303:03:043
22245998382cyclictest0-21swapper/302:53:203
22245998382cyclictest0-21swapper/302:43:053
22245998382cyclictest0-21swapper/302:31:053
22245998382cyclictest0-21swapper/302:23:293
22245998382cyclictest0-21swapper/302:13:293
22245998382cyclictest0-21swapper/302:13:073
22245998382cyclictest0-21swapper/302:03:323
22245998371cyclictest0-21swapper/304:23:163
22244998382cyclictest1086-21tune2fs01:58:242
22244998382cyclictest0-21swapper/206:33:202
22244998382cyclictest0-21swapper/206:13:122
22244998382cyclictest0-21swapper/205:28:232
22244998382cyclictest0-21swapper/205:13:252
22244998382cyclictest0-21swapper/205:08:222
22244998382cyclictest0-21swapper/204:58:192
22244998382cyclictest0-21swapper/204:43:242
22244998382cyclictest0-21swapper/204:06:182
22244998382cyclictest0-21swapper/203:43:232
22244998382cyclictest0-21swapper/203:36:142
22244998382cyclictest0-21swapper/203:33:042
22244998382cyclictest0-21swapper/202:18:292
22244998382cyclictest0-21swapper/202:11:022
22244998382cyclictest0-21swapper/201:38:322
22244998382cyclictest0-21swapper/201:33:312
22244998381cyclictest7519-21tune2fs02:13:222
22244998381cyclictest4067-21tune2fs05:53:142
22244998381cyclictest32632-21tune2fs04:28:162
22244998381cyclictest27828-21tune2fs05:33:142
22244998381cyclictest2308-21tune2fs04:33:162
22244998381cyclictest19802-21tune2fs03:58:312
22244998381cyclictest16980-21tune2fs06:23:132
22245998281cyclictest0-21swapper/306:33:113
22245998281cyclictest0-21swapper/304:33:163
22245998281cyclictest0-21swapper/302:48:273
22245998281cyclictest0-21swapper/301:58:243
22244997672cyclictest0-21swapper/203:23:162
22245997573cyclictest0-21swapper/306:48:123
22245997573cyclictest0-21swapper/305:43:143
22245997573cyclictest0-21swapper/302:43:213
22245997473cyclictest0-21swapper/306:59:003
22245997473cyclictest0-21swapper/305:03:143
22245997473cyclictest0-21swapper/302:36:063
22245997473cyclictest0-21swapper/302:36:063
22245997472cyclictest0-21swapper/305:33:223
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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