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2022-10-02 - 03:15

x86 Intel Core2 Quad @2400 MHz, Linux 3.2.46-rt67-32 (Profile)

Latency plot of system in rack #3, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100, highest latencies:
System rack3slot1.osadl.org (updated Sun Oct 02, 2022 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1123899126124cyclictest28720-21tune2fs16:07:032
1123899110102cyclictest29633-21tune2fs19:56:532
1123899110102cyclictest20017-21tune2fs17:02:032
1123899109102cyclictest2080-21tune2fs18:51:592
112389910492cyclictest0-21swapper/218:22:072
1123899104102cyclictest4348-21tune2fs18:57:022
1123899104102cyclictest13842-21tune2fs15:32:062
1123999103102cyclictest22687-21sed18:22:073
1123999103102cyclictest0-21swapper/320:51:473
1123999103102cyclictest0-21swapper/320:32:073
1123999103102cyclictest0-21swapper/318:57:023
1123999103102cyclictest0-21swapper/315:52:023
11238999082cyclictest26938-21tune2fs16:02:032
11238999071cyclictest0-21swapper/220:37:142
11238998981cyclictest28302-21tune2fs17:22:002
11238998972cyclictest0-21swapper/218:36:382
11238998882cyclictest0-21swapper/219:36:362
11238998882cyclictest0-21swapper/218:12:002
11238998782cyclictest0-21swapper/220:01:592
11238998782cyclictest0-21swapper/219:27:042
11238998782cyclictest0-21swapper/219:17:052
11238998782cyclictest0-21swapper/218:42:032
11238998771cyclictest0-21swapper/216:57:092
11238998671cyclictest0-21swapper/218:27:112
11239998482cyclictest0-21swapper/320:26:553
11239998482cyclictest0-21swapper/318:17:013
11238998482cyclictest30719-21tune2fs17:27:032
11238998482cyclictest11373-21tune2fs16:42:012
11239998382cyclictest0-21swapper/320:46:573
11239998382cyclictest0-21swapper/320:36:553
11239998382cyclictest0-21swapper/320:11:513
11239998382cyclictest0-21swapper/320:11:513
11239998382cyclictest0-21swapper/320:01:523
11239998382cyclictest0-21swapper/319:57:223
11239998382cyclictest0-21swapper/319:52:223
11239998382cyclictest0-21swapper/319:46:553
11239998382cyclictest0-21swapper/319:32:013
11239998382cyclictest0-21swapper/319:26:563
11239998382cyclictest0-21swapper/319:22:033
11239998382cyclictest0-21swapper/319:17:163
11239998382cyclictest0-21swapper/319:07:153
11239998382cyclictest0-21swapper/319:02:083
11239998382cyclictest0-21swapper/318:47:063
11239998382cyclictest0-21swapper/318:37:103
11239998382cyclictest0-21swapper/318:32:093
11239998382cyclictest0-21swapper/318:11:573
11239998382cyclictest0-21swapper/318:07:073
11239998382cyclictest0-21swapper/318:02:053
11239998382cyclictest0-21swapper/317:57:003
11239998382cyclictest0-21swapper/317:51:583
11239998382cyclictest0-21swapper/317:42:093
11239998382cyclictest0-21swapper/317:37:013
11239998382cyclictest0-21swapper/317:32:003
11239998382cyclictest0-21swapper/317:27:113
11239998382cyclictest0-21swapper/317:22:083
11239998382cyclictest0-21swapper/317:17:083
11239998382cyclictest0-21swapper/317:07:113
11239998382cyclictest0-21swapper/316:51:533
11239998382cyclictest0-21swapper/316:47:033
11239998382cyclictest0-21swapper/316:41:513
11239998382cyclictest0-21swapper/316:32:073
11239998382cyclictest0-21swapper/316:22:113
11239998382cyclictest0-21swapper/316:17:103
11239998382cyclictest0-21swapper/316:11:473
11239998382cyclictest0-21swapper/316:07:143
11239998382cyclictest0-21swapper/316:02:103
11239998382cyclictest0-21swapper/315:57:063
11239998382cyclictest0-21swapper/315:47:143
11239998382cyclictest0-21swapper/315:42:133
11239998382cyclictest0-21swapper/315:27:163
11238998382cyclictest0-21swapper/220:51:472
11238998382cyclictest0-21swapper/220:47:292
11238998382cyclictest0-21swapper/220:32:062
11238998382cyclictest0-21swapper/220:26:552
11238998382cyclictest0-21swapper/220:17:002
11238998382cyclictest0-21swapper/219:47:032
11238998382cyclictest0-21swapper/219:37:192
11238998382cyclictest0-21swapper/218:37:042
11238998382cyclictest0-21swapper/217:16:572
11238998382cyclictest0-21swapper/216:52:052
11238998382cyclictest0-21swapper/216:47:122
11238998382cyclictest0-21swapper/216:31:502
11238998382cyclictest0-21swapper/215:54:312
11238998382cyclictest0-21swapper/215:37:162
11238998381cyclictest406-21tune2fs17:32:022
11238998381cyclictest30860-21tune2fs16:12:002
11238998381cyclictest24292-21tune2fs17:11:582
11238998381cyclictest23451-21tune2fs19:41:532
11238998381cyclictest11963-21tune2fs15:27:052
11239998281cyclictest0-21swapper/318:27:023
11239998281cyclictest0-21swapper/317:47:013
11239998281cyclictest0-21swapper/317:11:583
11238998281cyclictest13063-21tune2fs18:01:592
11238998271cyclictest0-21swapper/215:57:062
11238997772cyclictest0-21swapper/220:41:512
11238997772cyclictest0-21swapper/219:06:372
11238997672cyclictest0-21swapper/218:50:522
11239997472cyclictest0-21swapper/320:16:513
11239997472cyclictest0-21swapper/318:51:593
11239997472cyclictest0-21swapper/315:32:183
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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