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2026-02-16 - 03:27
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot1.osadl.org (updated Mon Feb 16, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
509299103102cyclictest0-21swapper/318:59:333
5090998986cyclictest27537-21tune2fs20:24:311
5092998382cyclictest0-21swapper/323:49:093
5092998382cyclictest0-21swapper/323:29:253
5092998382cyclictest0-21swapper/323:24:233
5092998382cyclictest0-21swapper/323:24:233
5092998382cyclictest0-21swapper/323:14:213
5092998382cyclictest0-21swapper/323:05:213
5092998382cyclictest0-21swapper/322:39:203
5092998382cyclictest0-21swapper/322:39:123
5092998382cyclictest0-21swapper/322:29:183
5092998382cyclictest0-21swapper/322:29:123
5092998382cyclictest0-21swapper/322:14:253
5092998382cyclictest0-21swapper/322:14:253
5092998382cyclictest0-21swapper/321:19:343
5092998382cyclictest0-21swapper/321:19:153
5092998382cyclictest0-21swapper/321:09:333
5092998382cyclictest0-21swapper/321:09:153
5092998382cyclictest0-21swapper/320:49:033
5092998382cyclictest0-21swapper/320:29:393
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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