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2026-02-16 - 02:51
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack3slot1.osadl.org (updated Mon Feb 16, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
509299103102cyclictest0-21swapper/318:59:333
5090998986cyclictest27537-21tune2fs20:24:311
5092998382cyclictest0-21swapper/323:49:093
5092998382cyclictest0-21swapper/323:29:253
5092998382cyclictest0-21swapper/323:24:233
5092998382cyclictest0-21swapper/323:24:233
5092998382cyclictest0-21swapper/323:14:213
5092998382cyclictest0-21swapper/323:05:213
5092998382cyclictest0-21swapper/322:39:203
5092998382cyclictest0-21swapper/322:39:123
5092998382cyclictest0-21swapper/322:29:183
5092998382cyclictest0-21swapper/322:29:123
5092998382cyclictest0-21swapper/322:14:253
5092998382cyclictest0-21swapper/322:14:253
5092998382cyclictest0-21swapper/321:19:343
5092998382cyclictest0-21swapper/321:19:153
5092998382cyclictest0-21swapper/321:09:333
5092998382cyclictest0-21swapper/321:09:153
5092998382cyclictest0-21swapper/320:49:033
5092998382cyclictest0-21swapper/320:29:393
5092998382cyclictest0-21swapper/320:07:553
5092998382cyclictest0-21swapper/319:39:333
5092998382cyclictest0-21swapper/319:19:313
5092998382cyclictest0-21swapper/318:24:413
5090998382cyclictest0-21swapper/123:49:091
5090998382cyclictest0-21swapper/123:19:101
5090998382cyclictest0-21swapper/123:05:211
5090998382cyclictest0-21swapper/122:39:201
5090998382cyclictest0-21swapper/122:39:121
5090998382cyclictest0-21swapper/122:29:181
5090998382cyclictest0-21swapper/122:29:121
5090998382cyclictest0-21swapper/121:19:151
5090998382cyclictest0-21swapper/120:44:361
5090998382cyclictest0-21swapper/120:29:391
5090998382cyclictest0-21swapper/120:04:321
5090998382cyclictest0-21swapper/119:39:331
5090998382cyclictest0-21swapper/118:24:411
5090998381cyclictest29820-21tune2fs21:44:281
5090998381cyclictest23146-21tune2fs20:14:311
5090998381cyclictest22942-21tune2fs18:59:331
5090998371cyclictest8316-21tune2fs23:24:231
5090998371cyclictest8316-21tune2fs23:24:231
5092998281cyclictest0-21swapper/321:44:283
5092998281cyclictest0-21swapper/320:49:303
5092998281cyclictest0-21swapper/320:14:313
5092998281cyclictest0-21swapper/319:04:333
5090998281cyclictest0-21swapper/122:14:351
5090998281cyclictest0-21swapper/122:14:351
5090998271cyclictest0-21swapper/121:19:341
5090997876cyclictest0-21swapper/122:44:261
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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