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2023-01-28 - 10:33

x86 Intel Core2 Quad @2400 MHz, Linux 3.2.46-rt67-32 (Profile)

Latency plot of system in rack #3, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack3slot1.osadl.org (updated Sat Jan 28, 2023 00:43:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1277099125123cyclictest0-21swapper/313:55:173
1277099125123cyclictest0-21swapper/313:55:173
1276999123122cyclictest0-21swapper/213:55:172
1276999123122cyclictest0-21swapper/213:55:172
1276999115113cyclictest24005-21tune2fs14:05:082
1276999105103cyclictest3969-21tune2fs15:50:042
1276999104102cyclictest25581-21tune2fs15:25:102
1276999104102cyclictest15714-21tune2fs13:45:102
1277099103102cyclictest0-21swapper/317:40:003
1277099103102cyclictest0-21swapper/315:25:103
1277099103102cyclictest0-21swapper/314:05:083
1277099103102cyclictest0-21swapper/313:45:103
1276999103102cyclictest30129-21tune2fs15:35:102
12770999392cyclictest0-21swapper/318:20:143
12770999392cyclictest0-21swapper/315:35:103
12769998684cyclictest28190-21tune2fs14:15:092
12770998482cyclictest0-21swapper/315:10:053
12769998482cyclictest4385-21tune2fs14:35:082
12769998482cyclictest31808-21tune2fs16:55:062
12769998482cyclictest29294-21tune2fs18:05:032
12769998482cyclictest21141-21tune2fs16:30:082
12769998482cyclictest17526-21tune2fs13:50:102
12770998382cyclictest0-21swapper/319:00:073
12770998382cyclictest0-21swapper/318:49:583
12770998382cyclictest0-21swapper/318:40:103
12770998382cyclictest0-21swapper/318:15:083
12770998382cyclictest0-21swapper/318:05:033
12770998382cyclictest0-21swapper/317:59:453
12770998382cyclictest0-21swapper/317:46:033
12770998382cyclictest0-21swapper/317:34:593
12770998382cyclictest0-21swapper/317:20:123
12770998382cyclictest0-21swapper/317:15:103
12770998382cyclictest0-21swapper/317:00:123
12770998382cyclictest0-21swapper/316:35:133
12770998382cyclictest0-21swapper/316:30:083
12770998382cyclictest0-21swapper/316:20:143
12770998382cyclictest0-21swapper/316:19:503
12770998382cyclictest0-21swapper/316:10:063
12770998382cyclictest0-21swapper/316:00:053
12770998382cyclictest0-21swapper/315:55:463
12770998382cyclictest0-21swapper/315:50:043
12770998382cyclictest0-21swapper/315:30:123
12770998382cyclictest0-21swapper/315:15:403
12770998382cyclictest0-21swapper/315:05:173
12770998382cyclictest0-21swapper/315:00:073
12770998382cyclictest0-21swapper/314:55:153
12770998382cyclictest0-21swapper/314:25:173
12770998382cyclictest0-21swapper/314:00:273
12770998382cyclictest0-21swapper/313:39:563
12770998372cyclictest0-21swapper/314:30:153
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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