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2023-05-28 - 01:11

x86 Intel Core2 Quad @2400 MHz, Linux 3.2.46-rt67-32 (Profile)

Latency plot of system in rack #3, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack3slot1.osadl.org (updated Sat May 27, 2023 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1951399143142cyclictest1109-21munin-node02:57:132
1951499133132cyclictest0-21swapper/302:57:133
1951499103102cyclictest0-21swapper/303:22:063
1951499103102cyclictest0-21swapper/300:32:113
195139910392cyclictest0-21swapper/204:22:042
1951399103102cyclictest4863-21tune2fs00:32:112
1951399103102cyclictest11876-21munin-node03:22:062
19514999392cyclictest0-21swapper/304:22:053
19514998988cyclictest0-21swapper/300:27:113
19513998482cyclictest29544-21tune2fs04:02:012
19513998482cyclictest20767-21tune2fs03:42:032
19513998482cyclictest16403-21tail04:46:582
19514998382cyclictest0-21swapper/304:17:123
19514998382cyclictest0-21swapper/304:12:083
19514998382cyclictest0-21swapper/300:22:153
19513998382cyclictest0-21swapper/205:12:082
19513998382cyclictest0-21swapper/205:02:092
19513998382cyclictest0-21swapper/204:37:022
19513998382cyclictest0-21swapper/204:32:052
19513998382cyclictest0-21swapper/204:12:082
19513998382cyclictest0-21swapper/204:07:102
19513998382cyclictest0-21swapper/203:56:592
19513998382cyclictest0-21swapper/203:37:042
19513998382cyclictest0-21swapper/203:12:022
19513998382cyclictest0-21swapper/203:07:152
19513998382cyclictest0-21swapper/202:12:112
19513998382cyclictest0-21swapper/201:52:132
19513998382cyclictest0-21swapper/201:27:172
19513998382cyclictest0-21swapper/201:21:572
19513998382cyclictest0-21swapper/201:12:132
19513998382cyclictest0-21swapper/200:56:532
19513998382cyclictest0-21swapper/200:52:062
19513998382cyclictest0-21swapper/200:41:512
19513998382cyclictest0-21swapper/200:41:512
19513998382cyclictest0-21swapper/200:26:502
19513998382cyclictest0-21swapper/200:22:152
19513998382cyclictest0-21swapper/200:17:172
19513998382cyclictest0-21swapper/200:12:162
19513998382cyclictest0-21swapper/200:02:182
19513998382cyclictest0-21swapper/200:01:462
19513998381cyclictest8555-21tune2fs01:57:112
19513998381cyclictest31867-21tune2fs02:52:042
19513998381cyclictest29995-21tune2fs02:47:072
19513998381cyclictest2316-21tune2fs01:42:052
19513998381cyclictest23102-21tune2fs03:47:022
19513998381cyclictest20061-21tune2fs23:52:042
19513998372cyclictest10139-21tune2fs03:17:002
19513998371cyclictest0-21swapper/204:17:122
19514998281cyclictest0-21swapper/323:52:043
19514998281cyclictest0-21swapper/305:07:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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