You are here: Home / Projects / QA Farm Realtime / Latency plots / 
2021-01-27 - 10:39

Intel(R) Core(TM)2 Quad CPU @ 2.40GHz, Linux 3.2.46-rt67-32 (Profile)

Latency plot of system in rack #3, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack3slot1.osadl.org (updated Wed Jan 27, 2021 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1746799113112cyclictest0-21swapper/120:05:371
1746899103102cyclictest0-21swapper/220:05:372
1746799102100cyclictest0-21swapper/117:50:421
174679910199cyclictest7658-21tune2fs21:20:361
174679910199cyclictest30420-21munin-plugin-st18:20:341
17467999492cyclictest13705-21tune2fs20:15:361
17467999190cyclictest0-21swapper/119:40:551
17467998482cyclictest19638-21tune2fs21:55:311
17467998472cyclictest0-21swapper/120:55:381
17468998382cyclictest0-21swapper/221:55:382
17468998382cyclictest0-21swapper/221:46:152
17468998382cyclictest0-21swapper/221:40:292
17468998382cyclictest0-21swapper/221:35:302
17468998382cyclictest0-21swapper/221:31:132
17468998382cyclictest0-21swapper/221:20:332
17468998382cyclictest0-21swapper/221:06:072
17468998382cyclictest0-21swapper/220:55:442
17468998382cyclictest0-21swapper/220:45:322
17468998382cyclictest0-21swapper/220:40:292
17468998382cyclictest0-21swapper/220:30:332
17468998382cyclictest0-21swapper/219:55:342
17468998382cyclictest0-21swapper/219:40:382
17468998382cyclictest0-21swapper/219:35:542
17468998382cyclictest0-21swapper/219:30:502
17468998382cyclictest0-21swapper/219:25:372
17468998382cyclictest0-21swapper/219:05:482
17468998382cyclictest0-21swapper/218:55:502
17468998382cyclictest0-21swapper/218:52:422
17468998382cyclictest0-21swapper/218:40:382
17468998382cyclictest0-21swapper/218:21:342
17468998382cyclictest0-21swapper/218:15:382
17468998382cyclictest0-21swapper/218:11:302
17468998382cyclictest0-21swapper/217:55:392
17468998382cyclictest0-21swapper/217:30:392
17468998382cyclictest0-21swapper/217:20:442
17468998382cyclictest0-21swapper/216:58:422
17468998382cyclictest0-21swapper/216:55:292
17468998382cyclictest0-21swapper/216:45:482
17468998382cyclictest0-21swapper/216:40:522
17468998382cyclictest0-21swapper/216:35:402
17468998371cyclictest14076-21tune2fs17:40:412
17467998382cyclictest0-21swapper/121:35:351
17467998382cyclictest0-21swapper/121:30:371
17467998382cyclictest0-21swapper/121:05:371
17467998382cyclictest0-21swapper/120:50:401
17467998382cyclictest0-21swapper/120:45:431
17467998382cyclictest0-21swapper/120:40:441
17467998382cyclictest0-21swapper/120:40:441
17467998382cyclictest0-21swapper/119:15:451
17467998382cyclictest0-21swapper/119:00:471
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional