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2023-02-04 - 01:07

x86 Intel Core i7-X980 @3333 MHz, Linux 3.12.31-rt45 (Profile)

Latency plot of system in rack #3, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100, Linux 4.9.20-rt16, x86_64 highest latencies:
System rack3slot3.osadl.org (updated Fri Feb 03, 2023 12:46:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120501230irq/42-ahci0-21swapper/107:08:241
18908211195sleep70-21swapper/707:05:289
19758210994sleep40-21swapper/407:07:376
120501040irq/42-ahci0-21swapper/307:07:595
1115350950irq/52-eth0-rx-0-21swapper/507:05:307
12050930irq/42-ahci0-21swapper/207:08:524
1963127160sleep110-21swapper/1107:05:553
1973626453sleep100-21swapper/1007:07:192
1979326353sleep60-21swapper/607:08:038
12050630irq/42-ahci0-21swapper/807:08:3510
1992426159sleep90-21swapper/907:09:0711
1681725955sleep00-21swapper/007:05:090
2010399320cyclictest0-21swapper/007:29:240
2010399320cyclictest0-21swapper/007:13:140
20103993129cyclictest32068-21chrt07:22:100
20141992120cyclictest0-21swapper/1107:10:023
20141991918cyclictest0-21swapper/1109:20:483
2010399195cyclictest7474-21chrt08:16:400
2010399190cyclictest0-21swapper/008:09:100
20140991817cyclictest23051-1kworker/10:0H07:48:112
2013999181cyclictest28476-21latency_hist12:30:0011
2013999181cyclictest0-21swapper/912:10:1211
2013999181cyclictest0-21swapper/912:05:2711
2013999181cyclictest0-21swapper/910:10:0111
2013999181cyclictest0-21swapper/909:55:2211
2012699182cyclictest0-21swapper/309:16:115
2010399183cyclictest0-21swapper/010:11:530
20103991814cyclictest3945-21chrt08:13:150
20140991716cyclictest23051-1kworker/10:0H07:17:292
2014099170cyclictest98772sleep1012:03:162
2014099170cyclictest78882sleep1009:01:072
2014099170cyclictest76452sleep1008:19:032
2014099170cyclictest7242sleep1011:05:212
2014099170cyclictest56772sleep1011:10:582
2014099170cyclictest56772sleep1011:10:572
2014099170cyclictest5342chrt08:52:062
2014099170cyclictest52902sleep1010:26:412
2014099170cyclictest47712sleep1009:41:372
2014099170cyclictest40892sleep1007:30:092
2014099170cyclictest40582sleep1008:14:492
2014099170cyclictest326802sleep1008:08:372
2014099170cyclictest321362sleep1007:23:082
2014099170cyclictest316302sleep1012:32:192
2014099170cyclictest311792sleep1011:46:382
2014099170cyclictest309202sleep1011:03:092
2014099170cyclictest293322sleep1008:46:542
2014099170cyclictest290902sleep1008:05:012
2014099170cyclictest274682sleep1011:40:372
2014099170cyclictest271062chrt10:56:202
2014099170cyclictest267262sleep1010:11:512
2014099170cyclictest26692sleep1007:25:332
2014099170cyclictest262442chrt09:27:102
2014099170cyclictest251492sleep1007:56:252
2014099170cyclictest240672sleep1011:38:492
2014099170cyclictest23982chrt11:51:262
2014099170cyclictest231862sleep1010:08:162
2014099170cyclictest225162sleep1009:20:582
2014099170cyclictest217332sleep1007:54:242
2014099170cyclictest214412sleep1012:20:062
2014099170cyclictest188582sleep1009:15:572
2014099170cyclictest184372chrt08:32:162
2014099170cyclictest165752sleep1011:26:002
2014099170cyclictest164152sleep1010:44:432
2014099170cyclictest16182chrt10:22:282
2014099170cyclictest154892sleep1009:14:442
2014099170cyclictest140162sleep1008:25:262
2014099170cyclictest13932sleep1012:35:202
2014099170cyclictest133602sleep1012:06:162
2014099170cyclictest131682sleep1007:40:212
2014099170cyclictest129132sleep1011:20:342
2014099170cyclictest12050irq/42-ahci10:46:082
2014099170cyclictest12050irq/42-ahci10:30:422
2014099170cyclictest12050irq/42-ahci10:15:592
2014099170cyclictest12050irq/42-ahci10:00:332
2014099170cyclictest12050irq/42-ahci09:46:212
2014099170cyclictest119152sleep1010:35:302
2014099170cyclictest115492sleep1009:06:312
2014099170cyclictest115492sleep1009:06:312
2014099170cyclictest1115450irq/53-eth0-tx-12:10:252
2014099170cyclictest1115350irq/52-eth0-rx-12:25:212
2014099170cyclictest1115350irq/52-eth0-rx-11:30:052
2014099170cyclictest1115350irq/52-eth0-rx-11:15:132
2014099170cyclictest1115350irq/52-eth0-rx-10:50:272
2014099170cyclictest1115350irq/52-eth0-rx-09:35:132
2014099170cyclictest1115350irq/52-eth0-rx-09:30:142
2014099170cyclictest1115350irq/52-eth0-rx-08:55:302
2014099170cyclictest1115350irq/52-eth0-rx-08:40:132
2014099170cyclictest1115350irq/52-eth0-rx-07:10:302
2014099170cyclictest105502sleep1007:35:582
20139991716cyclictest0-21swapper/907:25:2211
2013999171cyclictest0-21swapper/909:40:2411
2013999170cyclictest0-21swapper/907:23:3411
20128991715cyclictest23177-21qemu-kvm10:08:197
2012699171cyclictest0-21swapper/312:30:115
2012699171cyclictest0-21swapper/312:16:105
2012699171cyclictest0-21swapper/312:10:035
2012699171cyclictest0-21swapper/312:00:455
2012699171cyclictest0-21swapper/311:43:315
2012699171cyclictest0-21swapper/311:37:475
2012699171cyclictest0-21swapper/311:25:285
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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