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2026-01-20 - 06:41
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot3.osadl.org (updated Tue Jan 20, 2026 00:46:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
128501210irq/42-ahci0-21swapper/119:08:521
16071210992sleep110-21swapper/1119:05:523
9918501080irq/53-eth0-rx-0-21swapper/219:09:014
16107210895sleep40-21swapper/419:06:216
9918501040irq/53-eth0-rx-0-21swapper/819:05:5010
9918501020irq/53-eth0-rx-0-21swapper/1019:09:202
12850930irq/42-ahci0-21swapper/319:08:455
991850920irq/53-eth0-rx-0-21swapper/919:06:2911
991850890irq/53-eth0-rx-0-21swapper/719:05:089
991850880irq/53-eth0-rx-0-21swapper/519:05:237
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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