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2024-03-02 - 00:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot3.osadl.org (updated Fri Mar 01, 2024 12:46:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18779501130irq/52-eth0-rx-0-21swapper/107:09:471
6188210995sleep90-21swapper/907:06:1011
5417210995sleep30-21swapper/307:05:405
6234210894sleep80-21swapper/807:06:4510
120501010irq/42-ahci0-21swapper/207:08:264
1877950950irq/52-eth0-rx-0-21swapper/507:07:437
1877950920irq/52-eth0-rx-0-21swapper/407:07:546
12050860irq/42-ahci0-21swapper/707:05:229
639325955sleep110-21swapper/1107:08:123
630225955sleep00-21swapper/007:07:370
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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