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2024-06-18 - 07:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot3.osadl.org (updated Tue Jun 18, 2024 00:46:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16238210995sleep50-21swapper/519:07:307
122501030irq/42-ahci0-21swapper/819:09:0310
122501010irq/42-ahci0-21swapper/119:09:091
1105350950irq/53-eth0-tx-0-21swapper/219:08:564
1645529286sleep70-21swapper/719:09:449
1105250920irq/52-eth0-rx-0-21swapper/419:05:306
12250860irq/42-ahci0-21swapper/319:09:095
1642727469sleep60-21swapper/619:09:198
1105350730irq/53-eth0-tx-0-21swapper/019:05:260
1612226453sleep110-21swapper/1119:06:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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