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2023-10-03 - 22:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot3.osadl.org (updated Tue Oct 03, 2023 12:46:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
127501080irq/42-ahci0-21swapper/207:08:234
13041210594sleep10-21swapper/107:07:311
127501040irq/42-ahci0-21swapper/807:10:0110
2035850910irq/52-eth0-rx-0-21swapper/907:05:1411
2035850880irq/52-eth0-rx-0-21swapper/507:05:207
1326828683sleep70-21swapper/707:09:489
12750860irq/42-ahci0-21swapper/307:06:525
12750790irq/42-ahci0-21swapper/407:05:276
1306626553sleep110-21swapper/1107:07:533
1302326557sleep100-21swapper/1007:07:162
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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