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2024-04-19 - 00:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot3.osadl.org (updated Thu Apr 18, 2024 12:46:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
8614210895sleep30-21swapper/307:06:485
8591210593sleep80-21swapper/807:06:2910
8569210290sleep50-21swapper/507:06:137
2224850980irq/44-eth0-rx-0-21swapper/207:08:124
11850940irq/42-ahci0-21swapper/107:09:591
887729186sleep40-21swapper/407:09:386
883429186sleep70-21swapper/707:09:059
2224850910irq/44-eth0-rx-0-21swapper/907:05:2511
871328575sleep110-21swapper/1107:08:093
861126953sleep00-21swapper/007:06:450
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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