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2024-07-27 - 03:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot3.osadl.org (updated Sat Jul 27, 2024 00:46:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15315210795sleep90-21swapper/919:07:2611
15284210391sleep60-21swapper/619:07:008
12250970irq/42-ahci0-21swapper/119:09:231
12250920irq/42-ahci0-21swapper/219:05:404
1105250920irq/52-eth0-rx-0-21swapper/319:05:035
12250880irq/42-ahci0-21swapper/419:06:486
12250830irq/42-ahci0-21swapper/719:08:379
1554528078sleep80-21swapper/819:09:5010
1105250730irq/52-eth0-rx-0-21swapper/1019:07:022
1526826453sleep50-21swapper/519:06:467
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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