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2026-05-20 - 12:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot3.osadl.org (updated Wed May 20, 2026 00:46:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501280irq/53-eth0-rx-0-21swapper/119:08:541
9918501130irq/53-eth0-rx-0-21swapper/419:07:226
25684210894sleep100-21swapper/1019:06:442
25659210893sleep20-21swapper/219:06:254
22803210891sleep60-21swapper/619:05:058
12850990irq/42-ahci0-21swapper/319:09:155
2576829585sleep50-21swapper/519:07:517
2573329282sleep90-21swapper/919:07:1911
991850910irq/53-eth0-rx-0-21swapper/819:06:5210
991850900irq/53-eth0-rx-0-21swapper/719:06:449
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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