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2025-01-21 - 22:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot3.osadl.org (updated Tue Jan 21, 2025 12:46:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7334210894sleep10-21swapper/107:06:451
7291210391sleep60-21swapper/607:06:158
4452210294sleep100-21swapper/1007:05:062
2013050960irq/52-eth0-rx-0-21swapper/207:08:534
2013150940irq/53-eth0-tx-0-21swapper/907:06:0611
2013050910irq/52-eth0-rx-0-21swapper/807:07:3010
2013050900irq/52-eth0-rx-0-21swapper/307:07:175
2013050890irq/52-eth0-rx-0-21swapper/1107:07:053
2013050870irq/52-eth0-rx-0-21swapper/507:05:237
2013050830irq/52-eth0-rx-0-21swapper/407:05:046
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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