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2024-09-12 - 23:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot3.osadl.org (updated Thu Sep 12, 2024 12:46:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
122501150irq/42-ahci0-21swapper/107:09:101
122501080irq/42-ahci0-21swapper/207:08:274
27343210791sleep00-21swapper/007:05:500
27317210793sleep80-21swapper/807:05:3410
27364210691sleep60-21swapper/607:06:088
27321210390sleep100-21swapper/1007:05:362
2771029087sleep70-21swapper/707:09:579
1105250900irq/52-eth0-rx-0-21swapper/307:07:555
1105250870irq/52-eth0-rx-0-21swapper/407:05:276
1105250840irq/52-eth0-rx-0-21swapper/507:05:297
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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