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2024-11-05 - 17:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Tue Nov 05, 2024 12:46:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
149501140irq/18-uhci_hcd0-21swapper/1107:05:353
1162501130irq/18-i801_smb0-21swapper/807:05:3410
126501110irq/42-ahci0-21swapper/107:09:081
1162501060irq/18-i801_smb0-21swapper/207:06:394
149501040irq/18-uhci_hcd0-21swapper/407:05:226
29633501020irq/52-eth0-rx-0-21swapper/307:09:365
116250970irq/18-i801_smb0-21swapper/507:05:477
2963350950irq/52-eth0-rx-0-21swapper/707:05:289
1770029078sleep60-21swapper/607:05:428
116250760irq/18-i801_smb0-21swapper/1007:06:242
1797327265sleep90-21swapper/907:08:3311
116250670irq/18-i801_smb0-21swapper/007:09:470
18179994614cyclictest0-21swapper/008:14:380
18221994429cyclictest0-21swapper/1108:15:123
18221994415cyclictest0-21swapper/1108:13:163
18179993931cyclictest0-21swapper/008:09:510
18221993514cyclictest0-21swapper/1109:27:213
18179993415cyclictest0-21swapper/008:16:300
1817999330cyclictest0-21swapper/010:17:270
1822199290cyclictest0-21swapper/1110:14:303
1821699220cyclictest1577-21awk07:30:018
1817999225cyclictest0-21swapper/008:27:400
1817999220cyclictest0-21swapper/009:13:480
1817999203cyclictest0-21swapper/010:41:240
1822099192cyclictest831ksoftirqd/1010:35:272
1821999192cyclictest0-21swapper/910:10:1311
1821999192cyclictest0-21swapper/907:35:2311
18216991916cyclictest21534-21qemu-kvm10:13:358
116150190irq/18-parport00-21swapper/411:20:376
116150190irq/18-parport00-21swapper/408:53:536
116150190irq/18-parport00-21swapper/408:53:536
18220991817cyclictest0-21swapper/1010:24:592
18220991817cyclictest0-21swapper/1009:55:282
18220991816cyclictest21099-21snmp_easybox.os08:40:122
18220991816cyclictest20190-21snmp_rack3slot912:20:132
18220991816cyclictest19135-21snmp_rack3slot907:10:122
18220991816cyclictest18517-21snmp_easybox.os10:05:112
18220991816cyclictest15116-21snmp_rack3slot911:26:382
18220991816cyclictest15116-21snmp_rack3slot911:26:382
18220991816cyclictest10779-21snmp_rack3slot907:40:142
1822099181cyclictest14950irq/18-uhci_hcd11:13:232
1822099181cyclictest13850irq/18-ehci_hcd12:35:492
1822099181cyclictest13850irq/18-ehci_hcd11:46:272
1822099181cyclictest12650irq/42-ahci09:17:142
1822099181cyclictest116250irq/18-i801_smb12:31:252
1821999181cyclictest28981-21basename10:20:0011
1821999181cyclictest1896-1kworker/9:2H10:09:1411
1821999181cyclictest0-21swapper/912:07:0911
1821999181cyclictest0-21swapper/911:43:0711
1821999181cyclictest0-21swapper/911:20:2911
1821999181cyclictest0-21swapper/907:40:2111
18216991816cyclictest21534-21qemu-kvm10:20:138
18216991816cyclictest21533-21qemu-kvm10:36:518
18216991816cyclictest21533-21qemu-kvm10:33:458
18216991816cyclictest21533-21qemu-kvm10:08:398
18214991816cyclictest21533-21qemu-kvm10:10:487
1817999184cyclictest0-21swapper/007:15:230
13850180irq/18-ehci_hcd0-21swapper/007:40:210
116150180irq/18-parport00-21swapper/007:11:490
18220991716cyclictest1737-21snmp_rack3slot910:25:142
18220991716cyclictest0-21swapper/1010:00:322
18220991715cyclictest3853-21iostat_ios07:30:192
18220991715cyclictest31745-21snmp_rack3slot907:25:122
18220991715cyclictest24817-21snmp_rack3slot908:00:112
18220991715cyclictest22700-21snmp_easybox.os10:55:112
18220991715cyclictest13013-21snmp_rack3slot910:40:162
1822099170cyclictest90812sleep1012:05:062
1822099170cyclictest88262sleep1007:37:362
1822099170cyclictest831ksoftirqd/1008:20:302
1822099170cyclictest831ksoftirqd/1008:05:152
1822099170cyclictest811rcuc/1011:50:102
1822099170cyclictest811rcuc/1011:50:102
1822099170cyclictest77912chrt11:15:482
1822099170cyclictest77912chrt11:15:482
1822099170cyclictest72962sleep1010:30:422
1822099170cyclictest67802sleep1012:00:182
1822099170cyclictest61232sleep1009:00:452
1822099170cyclictest3592sleep1008:10:162
1822099170cyclictest317622chrt09:36:252
1822099170cyclictest311202sleep1008:50:462
1822099170cyclictest311202sleep1008:50:462
1822099170cyclictest31122chrt11:55:172
1822099170cyclictest302302sleep1011:05:122
1822099170cyclictest2963350irq/52-eth0-rx-11:35:242
1822099170cyclictest2963350irq/52-eth0-rx-09:40:142
1822099170cyclictest2963350irq/52-eth0-rx-07:55:052
1822099170cyclictest2963350irq/52-eth0-rx-07:50:122
1822099170cyclictest2963350irq/52-eth0-rx-07:45:302
1822099170cyclictest293382sleep1011:02:592
1822099170cyclictest285622sleep1010:15:302
1822099170cyclictest281082sleep1009:31:132
1822099170cyclictest274802chrt08:45:442
1822099170cyclictest27172sleep1008:15:042
1822099170cyclictest250652sleep1010:11:302
1822099170cyclictest250422sleep1007:15:222
1822099170cyclictest245212sleep1011:40:152
1822099170cyclictest244412sleep1009:25:492
1822099170cyclictest236962sleep1012:25:562
1822099170cyclictest23532sleep1008:55:452
1822099170cyclictest218462chrt10:50:342
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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