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2023-05-28 - 08:47

x86 Intel Core i7-X980 @3333 MHz, Linux 3.12.31-rt45 (Profile)

Latency plot of system in rack #3, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sun May 28, 2023 00:46:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
10212123106sleep00-21swapper/019:07:440
8843501120irq/52-eth0-rx-0-21swapper/119:09:281
8843501080irq/52-eth0-rx-0-21swapper/419:08:196
1049210794sleep90-21swapper/919:08:0511
12250990irq/42-ahci0-21swapper/219:09:074
884350970irq/52-eth0-rx-0-21swapper/719:09:059
117729691sleep80-21swapper/819:09:0310
884350910irq/52-eth0-rx-0-21swapper/1019:07:142
12250850irq/42-ahci0-21swapper/319:09:095
3053327769sleep110-21swapper/1119:05:073
86026250sleep60-21swapper/619:05:388
884350610irq/52-eth0-rx-0-21swapper/519:06:427
136699300cyclictest16868-21chrt20:10:260
12250280irq/42-ahci0-21swapper/820:13:1010
12250280irq/42-ahci0-21swapper/220:13:084
136699260cyclictest0-21swapper/022:28:060
136699213cyclictest0-21swapper/020:09:430
136699213cyclictest0-21swapper/019:15:330
136699203cyclictest0-21swapper/023:00:420
136699203cyclictest0-21swapper/019:54:400
136699202cyclictest0-21swapper/021:20:320
136699202cyclictest0-21swapper/020:40:300
136699202cyclictest0-21swapper/020:15:280
136699202cyclictest0-21swapper/019:45:300
136699201cyclictest0-21swapper/021:50:180
136699201cyclictest0-21swapper/019:20:290
136699193cyclictest0-21swapper/022:30:180
136699193cyclictest0-21swapper/020:29:400
136699193cyclictest0-21swapper/020:21:100
136699192cyclictest0-21swapper/020:52:080
136699191cyclictest0-21swapper/023:40:340
136699191cyclictest0-21swapper/022:55:400
136699191cyclictest0-21swapper/022:15:340
136699191cyclictest0-21swapper/022:10:330
136699191cyclictest0-21swapper/021:40:330
136699191cyclictest0-21swapper/021:15:060
136699191cyclictest0-21swapper/021:05:020
136699191cyclictest0-21swapper/019:30:300
136699191cyclictest0-21swapper/000:10:340
136699190cyclictest0-21swapper/020:00:300
141299181cyclictest265022chrt22:38:412
141299180cyclictest103062sleep1020:02:352
140599181cyclictest2869-1kworker/9:0H20:08:5711
1402991816cyclictest30679-21snmp_rack3slot921:15:1810
1402991816cyclictest18070-21snmp_rack3slot920:57:2410
1402991816cyclictest17339-21perl22:25:2310
136699183cyclictest0-21swapper/023:48:440
136699183cyclictest0-21swapper/023:48:430
136699183cyclictest0-21swapper/020:35:180
136699183cyclictest0-21swapper/020:35:170
136699182cyclictest0-21swapper/022:50:360
136699182cyclictest0-21swapper/020:45:200
136699182cyclictest0-21swapper/020:34:000
136699182cyclictest0-21swapper/019:13:080
136699181cyclictest0-21swapper/023:10:320
136699181cyclictest0-21swapper/022:05:240
136699181cyclictest0-21swapper/021:55:200
136699181cyclictest0-21swapper/019:55:330
136699181cyclictest0-21swapper/019:29:350
136699181cyclictest0-21swapper/000:21:080
136699180cyclictest0-21swapper/023:55:350
136699180cyclictest0-21swapper/023:55:340
136699180cyclictest0-21swapper/023:50:380
136699180cyclictest0-21swapper/023:35:300
136699180cyclictest0-21swapper/022:45:370
136699180cyclictest0-21swapper/022:00:220
136699180cyclictest0-21swapper/021:30:310
136699180cyclictest0-21swapper/021:25:100
136699180cyclictest0-21swapper/021:10:300
136699180cyclictest0-21swapper/000:15:380
1413991715cyclictest0-21swapper/1121:08:423
1412991716cyclictest7070-1kworker/10:1H00:30:152
141299170cyclictest97412sleep1019:16:182
141299170cyclictest94752sleep1000:26:532
141299170cyclictest89792sleep1023:41:002
141299170cyclictest8292sleep1022:03:242
141299170cyclictest7902sleep1000:15:282
141299170cyclictest75772sleep1021:25:452
141299170cyclictest73082sleep1020:44:392
141299170cyclictest65502chrt19:56:342
141299170cyclictest51642sleep1022:54:182
141299170cyclictest51592sleep1000:20:302
141299170cyclictest4572sleep1020:35:152
141299170cyclictest4572sleep1020:35:142
141299170cyclictest44452sleep1022:06:262
141299170cyclictest41842sleep1019:10:282
141299170cyclictest321662sleep1020:31:512
141299170cyclictest316132sleep1019:46:462
141299170cyclictest308702sleep1000:11:262
141299170cyclictest305262sleep1023:27:362
141299170cyclictest305262sleep1023:27:352
141299170cyclictest29302chrt19:51:462
141299170cyclictest284812sleep1020:26:132
141299170cyclictest272052sleep1000:06:162
141299170cyclictest268682chrt23:22:212
141299170cyclictest261592sleep1021:10:062
141299170cyclictest259902sleep1021:53:482
141299170cyclictest249442sleep1020:22:502
141299170cyclictest246422sleep1021:05:292
141299170cyclictest245292chrt19:39:332
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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