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2024-04-27 - 14:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sat Apr 27, 2024 12:46:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12570210894sleep50-21swapper/507:05:527
12662210793sleep20-21swapper/207:07:014
11985210593sleep10-21swapper/107:05:371
118501000irq/42-ahci0-21swapper/707:08:489
1288529893sleep90-21swapper/907:09:2011
2224850960irq/44-eth0-rx-0-21swapper/307:06:435
2224850910irq/44-eth0-rx-0-21swapper/407:05:266
1268728577sleep110-21swapper/1107:07:223
1260426453sleep80-21swapper/807:06:2010
1121626354sleep100-21swapper/1007:05:212
1261726253sleep60-21swapper/607:06:298
1198425955sleep00-21swapper/007:05:360
1308599300cyclictest0-21swapper/1107:17:473
1308599300cyclictest0-21swapper/1107:17:463
1303899290cyclictest0-21swapper/008:26:370
1307999258cyclictest831ksoftirqd/1008:32:172
1307999252cyclictest831ksoftirqd/1010:17:152
1307999252cyclictest831ksoftirqd/1007:19:312
1307999252cyclictest831ksoftirqd/1007:19:312
1307999247cyclictest831ksoftirqd/1011:41:032
1307999247cyclictest831ksoftirqd/1007:59:512
1307999242cyclictest831ksoftirqd/1011:08:222
1307999222cyclictest831ksoftirqd/1010:59:422
1307999214cyclictest831ksoftirqd/1011:13:432
1307999214cyclictest831ksoftirqd/1008:15:592
1307999203cyclictest831ksoftirqd/1012:35:032
1307999203cyclictest831ksoftirqd/1012:30:022
1307999203cyclictest831ksoftirqd/1012:25:082
1307999203cyclictest831ksoftirqd/1012:20:022
1307999203cyclictest831ksoftirqd/1012:15:182
1307999203cyclictest831ksoftirqd/1012:10:042
1307999203cyclictest831ksoftirqd/1012:05:042
1307999203cyclictest831ksoftirqd/1012:00:162
1307999203cyclictest831ksoftirqd/1011:55:432
1307999203cyclictest831ksoftirqd/1011:50:062
1307999203cyclictest831ksoftirqd/1011:45:042
1307999203cyclictest831ksoftirqd/1011:35:072
1307999203cyclictest831ksoftirqd/1011:30:022
1307999203cyclictest831ksoftirqd/1011:25:092
1307999203cyclictest831ksoftirqd/1011:20:082
1307999203cyclictest831ksoftirqd/1011:15:032
1307999203cyclictest831ksoftirqd/1011:00:012
1307999203cyclictest831ksoftirqd/1010:50:022
1307999203cyclictest831ksoftirqd/1010:45:012
1307999203cyclictest831ksoftirqd/1010:40:122
1307999203cyclictest831ksoftirqd/1010:35:152
1307999203cyclictest831ksoftirqd/1010:30:022
1307999203cyclictest831ksoftirqd/1010:25:022
1307999203cyclictest831ksoftirqd/1010:20:092
1307999203cyclictest831ksoftirqd/1010:10:042
1307999203cyclictest831ksoftirqd/1010:10:032
1307999203cyclictest831ksoftirqd/1010:05:032
1307999203cyclictest831ksoftirqd/1010:00:042
1307999203cyclictest831ksoftirqd/1009:55:162
1307999203cyclictest831ksoftirqd/1009:50:102
1307999203cyclictest831ksoftirqd/1009:45:062
1307999203cyclictest831ksoftirqd/1009:40:132
1307999203cyclictest831ksoftirqd/1009:35:122
1307999203cyclictest831ksoftirqd/1009:30:052
1307999203cyclictest831ksoftirqd/1009:25:012
1307999203cyclictest831ksoftirqd/1009:20:052
1307999203cyclictest831ksoftirqd/1009:15:082
1307999203cyclictest831ksoftirqd/1009:10:062
1307999203cyclictest831ksoftirqd/1009:05:042
1307999203cyclictest831ksoftirqd/1009:00:132
1307999203cyclictest831ksoftirqd/1008:55:252
1307999203cyclictest831ksoftirqd/1008:50:022
1307999203cyclictest831ksoftirqd/1008:45:052
1307999203cyclictest831ksoftirqd/1008:40:012
1307999203cyclictest831ksoftirqd/1008:35:012
1307999203cyclictest831ksoftirqd/1008:25:082
1307999203cyclictest831ksoftirqd/1008:20:022
1307999203cyclictest831ksoftirqd/1008:10:062
1307999203cyclictest831ksoftirqd/1008:05:042
1307999203cyclictest831ksoftirqd/1008:00:042
1307999203cyclictest831ksoftirqd/1007:50:132
1307999203cyclictest831ksoftirqd/1007:45:062
1307999203cyclictest831ksoftirqd/1007:40:012
1307999203cyclictest831ksoftirqd/1007:35:192
1307999203cyclictest831ksoftirqd/1007:30:172
1307999203cyclictest831ksoftirqd/1007:25:032
1307999203cyclictest831ksoftirqd/1007:20:092
1307999203cyclictest831ksoftirqd/1007:20:092
1307999203cyclictest831ksoftirqd/1007:10:132
1308599184cyclictest0-21swapper/1110:50:233
1308599180cyclictest0-21swapper/1111:39:553
1307899181cyclictest3375-1kworker/9:0H09:25:3011
1307899181cyclictest3375-1kworker/9:0H08:49:1611
1307899181cyclictest0-21swapper/910:20:2311
1307899181cyclictest0-21swapper/910:08:5911
13077991816cyclictest4483-21snmp_rack3slot909:06:2310
13077991816cyclictest3963-21users08:20:3810
13077991816cyclictest3299-21perl09:50:1910
13077991816cyclictest30246-21snmp_rack3slot907:30:1710
13077991816cyclictest10677-21sensors_temp08:30:2810
13070991816cyclictest25587-21qemu-kvm08:08:257
13064991816cyclictest29407-21python09:40:286
1308599173cyclictest0-21swapper/1111:40:233
1308599170cyclictest0-21swapper/1110:08:413
1308599170cyclictest0-21swapper/1109:28:393
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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