You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2023-02-06 - 14:13

x86 Intel Core i7-X980 @3333 MHz, Linux 3.12.31-rt45 (Profile)

Latency plot of system in rack #3, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Mon Feb 06, 2023 12:46:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12128210490sleep110-21swapper/1107:07:203
12056210390sleep40-21swapper/407:06:246
12050960irq/42-ahci0-21swapper/107:09:071
1115350940irq/52-eth0-rx-0-21swapper/207:05:324
1115450900irq/53-eth0-tx-0-21swapper/707:08:549
1115350890irq/52-eth0-rx-0-21swapper/507:05:367
1115450800irq/53-eth0-tx-0-21swapper/1007:06:252
13250780irq/18-ehci_hcd0-21swapper/307:09:235
129250740irq/18-parport00-21swapper/807:09:2310
915126958sleep60-21swapper/607:05:028
1209926855sleep00-21swapper/007:06:580
918526656sleep90-21swapper/907:05:0511
12481993517cyclictest0-21swapper/010:28:420
12481993029cyclictest0-21swapper/007:27:580
12481992914cyclictest52272sleep010:10:400
12481992914cyclictest52272sleep010:10:400
1253199260cyclictest0-21swapper/1109:20:363
12531992513cyclictest54102sleep1110:13:173
12531992513cyclictest54102sleep1110:13:163
14950200irq/18-uhci_hcd0-21swapper/407:10:266
14950200irq/18-uhci_hcd0-21swapper/407:10:266
12530991917cyclictest811rcuc/1012:10:032
1253099181cyclictest1115350irq/52-eth0-rx-07:55:152
1252999181cyclictest5688-1kworker/9:0H11:49:2311
1252999181cyclictest26720-21kworker/9:208:45:0111
1252999181cyclictest0-21swapper/910:05:4911
12519991816cyclictest4140-21qemu-kvm09:26:158
12518991816cyclictest25044-21qemu-kvm08:10:177
12518991815cyclictest25043-21qemu-kvm08:20:207
1248199182cyclictest0-21swapper/010:30:210
1248199182cyclictest0-21swapper/008:30:190
12481991817cyclictest12985-21munin-node07:10:210
12481991817cyclictest12985-21munin-node07:10:210
1248199180cyclictest0-21swapper/008:08:210
13250170irq/18-ehci_hcd0-21swapper/007:15:010
1253199170cyclictest0-21swapper/1107:30:373
12530991716cyclictest24772sleep1011:36:492
12530991716cyclictest12482-1kworker/10:1H11:25:202
12530991716cyclictest0-21swapper/1009:04:492
12530991716cyclictest0-21swapper/1008:40:572
1253099170cyclictest98722sleep1011:48:012
1253099170cyclictest93232sleep1012:30:302
1253099170cyclictest92892sleep1011:00:442
1253099170cyclictest90072sleep1010:17:392
1253099170cyclictest86462sleep1008:30:152
1253099170cyclictest66992sleep1007:42:452
1253099170cyclictest65852sleep1012:27:072
1253099170cyclictest60892sleep1011:41:002
1253099170cyclictest52662sleep1010:11:152
1253099170cyclictest52662sleep1010:11:152
1253099170cyclictest312982chrt11:32:372
1253099170cyclictest310722sleep1010:05:142
1253099170cyclictest285062sleep1008:10:362
1253099170cyclictest271092sleep1010:41:062
1253099170cyclictest260342sleep1009:55:022
1253099170cyclictest260342sleep1009:55:012
1253099170cyclictest255032sleep1008:53:302
1253099170cyclictest220952sleep1009:46:242
1253099170cyclictest220952sleep1009:46:242
1253099170cyclictest21842sleep1008:20:262
1253099170cyclictest216942chrt08:46:172
1253099170cyclictest215082sleep1010:35:172
1253099170cyclictest214622sleep1008:04:492
1253099170cyclictest212652sleep1009:41:592
1253099170cyclictest20822sleep1010:52:432
1253099170cyclictest202862sleep1011:16:102
1253099170cyclictest198242chrt10:30:532
1253099170cyclictest196142sleep1012:00:282
1253099170cyclictest176092sleep1009:36:462
1253099170cyclictest171992sleep1011:58:392
1253099170cyclictest169252sleep1009:34:222
1253099170cyclictest167142sleep1011:11:572
1253099170cyclictest161632chrt10:25:402
1253099170cyclictest15842sleep1007:35:222
1253099170cyclictest139592sleep1012:38:192
1253099170cyclictest135392sleep1011:53:152
1253099170cyclictest131022sleep1009:26:452
1253099170cyclictest125212sleep1010:20:392
1253099170cyclictest122212sleep1009:21:572
1253099170cyclictest12050irq/42-ahci10:47:282
1253099170cyclictest12050irq/42-ahci09:10:252
1253099170cyclictest12050irq/42-ahci08:08:222
1253099170cyclictest12050irq/42-ahci07:10:182
1253099170cyclictest12050irq/42-ahci07:10:172
1253099170cyclictest115522sleep1008:35:032
1253099170cyclictest1115350irq/52-eth0-rx-11:05:252
1253099170cyclictest1115350irq/52-eth0-rx-10:00:282
1253099170cyclictest1115350irq/52-eth0-rx-09:50:262
1253099170cyclictest1115350irq/52-eth0-rx-09:05:072
1253099170cyclictest1115350irq/52-eth0-rx-08:55:052
1253099170cyclictest1115350irq/52-eth0-rx-08:25:342
1253099170cyclictest1115350irq/52-eth0-rx-07:45:142
1253099170cyclictest1115350irq/52-eth0-rx-07:33:272
1253099170cyclictest110362sleep1007:50:122
1252999170cyclictest6807-21munin-run12:30:0111
1252999170cyclictest0-21swapper/912:01:4311
1252999170cyclictest0-21swapper/909:19:0411
1252999170cyclictest0-21swapper/908:31:1511
1252999170cyclictest0-21swapper/908:26:2411
1252999170cyclictest0-21swapper/907:15:3111
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional