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2021-10-16 - 14:10

Intel(R) Core(TM) i7 CPU X 980 @ 3.33GHz, Linux 3.12.31-rt45 (Profile)

Latency plot of system in rack #3, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sat Oct 16, 2021 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4238501090irq/52-eth0-rx-0-21swapper/106:51:171
4261210699sleep20-21swapper/206:52:564
3896210693sleep80-21swapper/806:48:4910
4001210592sleep60-21swapper/606:50:128
979210391sleep110-21swapper/1106:48:043
423850960irq/52-eth0-rx-0-21swapper/306:50:005
423850920irq/52-eth0-rx-0-21swapper/706:52:569
399528978sleep00-21swapper/006:50:060
394128976sleep100-21swapper/1006:49:282
423850880irq/52-eth0-rx-0-21swapper/506:48:107
413228078sleep90-21swapper/906:51:1511
423127674sleep40-21swapper/406:52:346
4414993818cyclictest0-21swapper/1109:51:193
436299320cyclictest0-21swapper/007:11:090
441499300cyclictest0-21swapper/1109:53:273
4384992415cyclictest2281-21snmpd07:10:434
4362992422cyclictest2660-21runrttasks08:07:300
4384992214cyclictest2281-21snmpd08:38:074
441499210cyclictest0-21swapper/1108:02:103
441299192cyclictest0-21swapper/910:03:1611
440099192cyclictest0-21swapper/412:09:436
440099192cyclictest0-21swapper/410:37:506
440099190cyclictest0-21swapper/407:04:426
441499180cyclictest0-21swapper/1107:54:143
4413991817cyclictest12341-1kworker/10:1H07:14:342
4413991817cyclictest0-21swapper/1008:47:032
441399181cyclictest423850irq/52-eth0-rx-10:04:462
441399181cyclictest180562chrt09:22:382
441399181cyclictest12350irq/42-ahci10:33:272
441399181cyclictest12350irq/42-ahci07:51:202
441399181cyclictest12350irq/42-ahci06:59:392
441299181cyclictest30521-1kworker/9:0H10:21:0611
441299181cyclictest0-21swapper/912:13:1211
441299181cyclictest0-21swapper/912:04:3611
441299181cyclictest0-21swapper/911:38:0611
441299181cyclictest0-21swapper/911:36:1111
441299181cyclictest0-21swapper/911:28:1311
441299181cyclictest0-21swapper/910:48:0511
441299181cyclictest0-21swapper/910:48:0511
441299181cyclictest0-21swapper/910:43:0611
441299181cyclictest0-21swapper/909:53:1311
441299181cyclictest0-21swapper/909:03:0811
441299181cyclictest0-21swapper/908:30:4411
441299181cyclictest0-21swapper/907:58:3011
441299181cyclictest0-21swapper/907:44:3511
441299181cyclictest0-21swapper/907:38:2711
441299181cyclictest0-21swapper/907:33:3111
4401991816cyclictest4121-21qemu-kvm07:28:587
440099182cyclictest0-21swapper/411:37:486
440099182cyclictest0-21swapper/411:14:296
440099182cyclictest0-21swapper/409:39:326
440099182cyclictest0-21swapper/407:59:206
440099182cyclictest0-21swapper/407:51:266
440099182cyclictest0-21swapper/407:40:396
440099182cyclictest0-21swapper/407:15:586
440099182cyclictest0-21swapper/407:01:166
440099181cyclictest0-21swapper/410:33:186
440099181cyclictest0-21swapper/409:18:096
440099181cyclictest0-21swapper/407:37:476
440099181cyclictest0-21swapper/407:19:226
440099181cyclictest0-21swapper/406:57:526
436299180cyclictest0-21swapper/008:01:370
4413991716cyclictest0-21swapper/1009:58:052
441399170cyclictest95032sleep1012:07:502
441399170cyclictest94602sleep1007:39:302
441399170cyclictest90902sleep1011:22:592
441399170cyclictest82112sleep1009:53:042
441399170cyclictest80182chrt12:03:142
441399170cyclictest65132chrt08:21:332
441399170cyclictest58132sleep1007:34:182
441399170cyclictest4382sleep1010:24:072
441399170cyclictest423850irq/52-eth0-rx-12:18:102
441399170cyclictest423850irq/52-eth0-rx-12:13:082
441399170cyclictest423850irq/52-eth0-rx-11:18:422
441399170cyclictest423850irq/52-eth0-rx-11:03:112
441399170cyclictest423850irq/52-eth0-rx-09:23:122
441399170cyclictest423850irq/52-eth0-rx-08:58:012
441399170cyclictest423850irq/52-eth0-rx-08:55:302
441399170cyclictest423850irq/52-eth0-rx-08:14:462
441399170cyclictest423850irq/52-eth0-rx-08:14:462
441399170cyclictest423850irq/52-eth0-rx-08:08:062
441399170cyclictest423850irq/52-eth0-rx-08:08:062
441399170cyclictest423850irq/52-eth0-rx-08:03:152
441399170cyclictest423850irq/52-eth0-rx-07:57:572
441399170cyclictest423850irq/52-eth0-rx-07:53:162
441399170cyclictest423850irq/52-eth0-rx-06:56:142
441399170cyclictest36272sleep1009:43:392
441399170cyclictest325352sleep1009:41:162
441399170cyclictest305162chrt11:07:582
441399170cyclictest302982sleep1011:51:132
441399170cyclictest295072sleep1010:22:302
441399170cyclictest287352sleep1009:34:152
441399170cyclictest282292sleep1008:49:232
441399170cyclictest263052sleep1011:02:102
441399170cyclictest263052sleep1011:02:102
441399170cyclictest256562sleep1010:14:302
441399170cyclictest243622chrt07:18:052
441399170cyclictest238532sleep1009:28:142
441399170cyclictest236232sleep1011:42:482
441399170cyclictest23222sleep1007:32:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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