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2023-03-28 - 08:32

x86 Intel Core i7-X980 @3333 MHz, Linux 3.12.31-rt45 (Profile)

Latency plot of system in rack #3, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100, highest latencies:
System rack3slot3.osadl.org (updated Tue Mar 28, 2023 00:46:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30409210896sleep90-21swapper/919:07:4111
30356210894sleep30-21swapper/319:06:595
30276210592sleep10-21swapper/119:05:571
121501010irq/42-ahci0-21swapper/219:08:504
1491850960irq/44-eth0-rx-0-21swapper/419:06:286
1491850920irq/44-eth0-rx-0-21swapper/519:06:007
12150920irq/42-ahci0-21swapper/719:08:389
3043828576sleep80-21swapper/819:08:0410
3030627567sleep110-21swapper/1119:06:193
3041926553sleep60-21swapper/619:07:508
3073599610cyclictest0-21swapper/022:13:560
3033826055sleep00-21swapper/019:06:440
3033525955sleep100-21swapper/1019:06:422
3073599440cyclictest0-21swapper/022:09:530
30735993819cyclictest0-21swapper/019:27:210
3073599310cyclictest0-21swapper/019:30:180
3073599310cyclictest0-21swapper/019:13:570
1491850280irq/44-eth0-rx-0-21swapper/319:30:135
30756992524cyclictest12150irq/42-ahci22:13:566
30784992214cyclictest0-21swapper/1122:21:553
30783991918cyclictest0-21swapper/1022:15:262
3077699192cyclictest0-21swapper/921:10:0111
3077699192cyclictest0-21swapper/920:20:0111
3077699190cyclictest0-21swapper/922:13:2611
30784991816cyclictest26983-21munin-node00:10:283
30783991817cyclictest0-21swapper/1000:35:302
3078399181cyclictest12150irq/42-ahci20:57:052
3078399181cyclictest12150irq/42-ahci20:08:502
3078399181cyclictest12150irq/42-ahci19:22:482
3078399180cyclictest12150irq/42-ahci22:27:592
30776991816cyclictest21538-21smartctl21:05:2711
30776991816cyclictest13242-21grep20:55:1611
3077699181cyclictest0-21swapper/922:50:2411
3077699181cyclictest0-21swapper/921:40:1911
30770991816cyclictest22359-21qemu-kvm21:20:138
30770991816cyclictest22359-21qemu-kvm21:20:138
30770991816cyclictest22359-21qemu-kvm21:08:368
30770991816cyclictest22358-21qemu-kvm21:10:138
30741991816cyclictest2339-21snmpd19:43:434
30783991716cyclictest1908-1kworker/10:0H23:40:482
30783991716cyclictest1908-1kworker/10:0H23:25:552
30783991716cyclictest0-21swapper/1023:15:042
30783991715cyclictest9950-21snmp_rack3slot921:35:152
30783991715cyclictest26166-21snmp_easybox.os20:30:122
3078399170cyclictest9792sleep1020:40:042
3078399170cyclictest90052sleep1000:30:312
3078399170cyclictest90052sleep1000:30:302
3078399170cyclictest72822chrt20:03:352
3078399170cyclictest70662sleep1023:00:212
3078399170cyclictest66062sleep1019:15:422
3078399170cyclictest61682sleep1000:25:532
3078399170cyclictest36212sleep1019:58:472
3078399170cyclictest308482chrt23:30:592
3078399170cyclictest299022sleep1022:00:482
3078399170cyclictest28522sleep1022:10:142
3078399170cyclictest276122sleep1000:11:042
3078399170cyclictest275842sleep1022:45:062
3078399170cyclictest274322sleep1019:45:212
3078399170cyclictest258642sleep1021:11:082
3078399170cyclictest254542sleep1021:55:242
3078399170cyclictest253872sleep1020:26:392
3078399170cyclictest253772chrt22:40:172
3078399170cyclictest25052chrt22:55:062
3078399170cyclictest248062sleep1019:40:452
3078399170cyclictest227612sleep1000:05:272
3078399170cyclictest223052sleep1021:08:062
3078399170cyclictest203142chrt22:35:052
3078399170cyclictest202982chrt00:00:502
3078399170cyclictest186472sleep1021:02:422
3078399170cyclictest186072sleep1019:35:202
3078399170cyclictest185952sleep1022:30:282
3078399170cyclictest18112sleep1019:13:422
3078399170cyclictest177672chrt19:33:562
3078399170cyclictest16762sleep1022:51:302
3078399170cyclictest164132chrt23:12:212
3078399170cyclictest153922sleep1021:41:232
3078399170cyclictest1491950irq/45-eth0-tx-20:10:312
3078399170cyclictest1491850irq/44-eth0-rx-23:55:272
3078399170cyclictest1491850irq/44-eth0-rx-23:50:222
3078399170cyclictest1491850irq/44-eth0-rx-23:35:262
3078399170cyclictest1491850irq/44-eth0-rx-23:21:062
3078399170cyclictest1491850irq/44-eth0-rx-21:50:252
3078399170cyclictest1491850irq/44-eth0-rx-21:25:222
3078399170cyclictest1491850irq/44-eth0-rx-21:20:292
3078399170cyclictest1491850irq/44-eth0-rx-21:20:292
3078399170cyclictest1491850irq/44-eth0-rx-20:50:132
3078399170cyclictest1491850irq/44-eth0-rx-20:35:162
3078399170cyclictest1491850irq/44-eth0-rx-20:15:222
3078399170cyclictest1491850irq/44-eth0-rx-19:51:462
3078399170cyclictest1491850irq/44-eth0-rx-00:20:572
3078399170cyclictest122372sleep1022:21:032
3078399170cyclictest12150irq/42-ahci23:05:202
3078399170cyclictest12150irq/42-ahci21:46:332
3078399170cyclictest12150irq/42-ahci21:32:102
3078399170cyclictest12150irq/42-ahci20:20:012
3078399170cyclictest12150irq/42-ahci19:26:552
3078399170cyclictest11832sleep1022:06:382
30776991716cyclictest22965-21smartctl23:20:2711
30776991716cyclictest0-21swapper/923:15:2411
30776991715cyclictest9409-21logger22:20:0711
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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