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2022-08-20 - 05:35

x86 Intel Core i7-X980 @3333 MHz, Linux 3.12.31-rt45 (Profile)

Latency plot of system in rack #3, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100, highest latencies:
System rack3slot3.osadl.org (updated Sat Aug 20, 2022 00:46:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
610211194sleep100-21swapper/1019:07:152
610211194sleep100-21swapper/1019:07:152
617211096sleep30-21swapper/319:07:205
617211096sleep30-21swapper/319:07:205
520210391sleep60-21swapper/619:06:118
520210391sleep60-21swapper/619:06:118
5413501020irq/52-eth0-rx-0-21swapper/419:08:426
5413501020irq/52-eth0-rx-0-21swapper/419:08:426
541350970irq/52-eth0-rx-0-21swapper/119:09:121
541350970irq/52-eth0-rx-0-21swapper/119:09:121
80929390sleep70-21swapper/719:09:139
80929390sleep70-21swapper/719:09:129
541350930irq/52-eth0-rx-0-21swapper/919:07:2111
541350930irq/52-eth0-rx-0-21swapper/919:07:2111
12450920irq/42-ahci0-21swapper/219:08:444
12450920irq/42-ahci0-21swapper/219:08:444
47728980sleep80-21swapper/819:05:3710
47728980sleep80-21swapper/819:05:3710
541350880irq/52-eth0-rx-0-21swapper/1119:06:173
541350880irq/52-eth0-rx-0-21swapper/1119:06:173
541350820irq/52-eth0-rx-0-21swapper/519:05:287
541350820irq/52-eth0-rx-0-21swapper/519:05:287
50025853sleep00-21swapper/019:05:540
50025853sleep00-21swapper/019:05:530
99499480cyclictest0-21swapper/022:09:490
99499440cyclictest0-21swapper/022:10:020
101299320cyclictest0-21swapper/1122:10:273
101299300cyclictest0-21swapper/1119:27:193
1004993029cyclictest541350irq/52-eth0-rx-19:19:085
1004993029cyclictest541350irq/52-eth0-rx-19:19:085
994992927cyclictest0-21swapper/019:19:230
994992927cyclictest0-21swapper/019:19:230
101199258cyclictest831ksoftirqd/1022:43:522
101199258cyclictest831ksoftirqd/1021:53:262
101199258cyclictest831ksoftirqd/1021:53:252
1005992524cyclictest12450irq/42-ahci19:19:136
1005992524cyclictest12450irq/42-ahci19:19:136
101199248cyclictest831ksoftirqd/1023:03:292
101199247cyclictest831ksoftirqd/1019:20:172
101199247cyclictest831ksoftirqd/1019:20:172
994991918cyclictest0-21swapper/020:29:360
101199192cyclictest831ksoftirqd/1023:55:192
101199192cyclictest831ksoftirqd/1021:20:182
101099192cyclictest0-21swapper/922:35:2211
100799191cyclictest0-21swapper/619:44:558
1011991817cyclictest831ksoftirqd/1021:10:222
1011991817cyclictest0-21swapper/1022:33:332
1011991817cyclictest0-21swapper/1019:26:212
1011991816cyclictest0-21swapper/1019:58:122
101199181cyclictest831ksoftirqd/1023:15:162
101199181cyclictest831ksoftirqd/1022:35:012
101199181cyclictest831ksoftirqd/1022:20:252
101199181cyclictest831ksoftirqd/1021:05:142
101199181cyclictest831ksoftirqd/1020:59:022
101199181cyclictest831ksoftirqd/1020:50:322
101199181cyclictest831ksoftirqd/1020:30:312
101199181cyclictest831ksoftirqd/1019:40:012
101199181cyclictest831ksoftirqd/1019:10:172
101199181cyclictest831ksoftirqd/1000:21:442
101199181cyclictest831ksoftirqd/1000:21:442
101199181cyclictest541350irq/52-eth0-rx-20:35:192
101199181cyclictest541350irq/52-eth0-rx-00:28:122
101199181cyclictest12450irq/42-ahci00:15:172
101099181cyclictest24355-1kworker/9:0H21:29:2011
101099181cyclictest24355-1kworker/9:0H21:21:1811
101099181cyclictest0-21swapper/923:10:2811
101099181cyclictest0-21swapper/900:20:3711
101099181cyclictest0-21swapper/900:20:3711
1007991816cyclictest730-21qemu-kvm19:23:108
1007991816cyclictest730-21qemu-kvm19:23:108
1007991816cyclictest729-21qemu-kvm19:39:558
1007991816cyclictest729-21qemu-kvm19:18:158
1007991816cyclictest729-21qemu-kvm19:18:158
1007991816cyclictest4162-21qemu-kvm22:35:148
1007991816cyclictest4162-21qemu-kvm22:34:038
1007991816cyclictest4162-21qemu-kvm22:18:308
1007991816cyclictest4162-21qemu-kvm22:08:408
1007991816cyclictest4161-21qemu-kvm22:44:118
1007991816cyclictest25069-21qemu-kvm21:08:178
1007991816cyclictest25068-21qemu-kvm21:36:048
1007991816cyclictest13627-21qemu-kvm20:16:468
1007991816cyclictest13627-21qemu-kvm20:08:408
1007991816cyclictest13626-21qemu-kvm20:41:038
994991713cyclictest16925-21nscd20:16:060
1011991716cyclictest831ksoftirqd/1021:35:002
1011991716cyclictest831ksoftirqd/1020:00:032
1011991716cyclictest0-21swapper/1023:40:242
1011991716cyclictest0-21swapper/1023:20:182
1011991716cyclictest0-21swapper/1022:15:122
1011991716cyclictest0-21swapper/1021:40:442
1011991716cyclictest0-21swapper/1021:30:182
1011991716cyclictest0-21swapper/1020:48:402
1011991716cyclictest0-21swapper/1020:40:162
1011991716cyclictest0-21swapper/1020:15:012
1011991716cyclictest0-21swapper/1000:10:192
1011991716cyclictest0-21swapper/1000:05:242
1011991716cyclictest0-21swapper/1000:05:242
101199170cyclictest831ksoftirqd/1023:50:132
101199170cyclictest831ksoftirqd/1023:45:182
101199170cyclictest831ksoftirqd/1023:35:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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