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2024-03-02 - 07:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot3.osadl.org (updated Sat Mar 02, 2024 00:46:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17622211095sleep90-21swapper/919:07:2111
17627210991sleep00-21swapper/019:07:240
17648210795sleep30-21swapper/319:07:395
17525210492sleep70-21swapper/719:06:079
1878050990irq/53-eth0-tx-0-21swapper/219:05:364
1784829287sleep10-21swapper/119:09:371
1469728574sleep80-21swapper/819:05:0810
1782828078sleep100-21swapper/1019:09:222
14850760irq/18-uhci_hcd0-21swapper/519:09:107
12050700irq/42-ahci0-21swapper/419:08:536
1758825955sleep60-21swapper/619:06:538
1470025955sleep110-21swapper/1119:05:113
1801999320cyclictest0-21swapper/1121:24:103
1801899192cyclictest1877950irq/52-eth0-rx-21:05:252
1801799192cyclictest0-21swapper/919:55:0211
18018991817cyclictest0-21swapper/1022:10:442
18018991817cyclictest0-21swapper/1021:50:462
18018991817cyclictest0-21swapper/1021:50:462
18018991817cyclictest0-21swapper/1020:56:112
18018991817cyclictest0-21swapper/1020:00:332
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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