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2024-06-25 - 07:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot3.osadl.org (updated Tue Jun 25, 2024 00:46:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
122501130irq/42-ahci0-21swapper/119:09:371
122501110irq/42-ahci0-21swapper/219:05:274
16059210894sleep30-21swapper/319:06:405
15992210895sleep100-21swapper/1019:05:472
16319210593sleep40-21swapper/419:09:316
1105250930irq/52-eth0-rx-0-21swapper/1119:07:263
1606927970sleep90-21swapper/919:06:4611
1318827363sleep60-21swapper/619:05:078
1608826953sleep00-21swapper/019:07:010
1105250690irq/52-eth0-rx-0-21swapper/819:07:0610
1614126354sleep70-21swapper/719:07:459
1105250630irq/52-eth0-rx-0-21swapper/519:05:577
16461993517cyclictest0-21swapper/020:10:400
16461993517cyclictest0-21swapper/020:10:390
1646199330cyclictest0-21swapper/019:28:030
1646199270cyclictest0-21swapper/019:11:510
16461992322cyclictest0-21swapper/021:14:010
16482992120cyclictest12250irq/42-ahci21:13:555
16461992120cyclictest0-21swapper/022:09:540
16461992120cyclictest0-21swapper/020:21:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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