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2025-07-06 - 03:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot3.osadl.org (updated Sun Jul 06, 2025 00:46:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
146919934385223438518cyclictest0-21swapper/1120:25:163
146559934353793435369cyclictest0-21swapper/321:21:185
146639934353633435349cyclictest0-21swapper/421:21:186
146429934353453435330cyclictest0-21swapper/021:21:180
146769934353173435310cyclictest0-21swapper/621:21:198
146699934353103435304cyclictest6228-21qemu-kvm21:21:197
146809934352993435294cyclictest0-21swapper/721:21:189
146449934352433435234cyclictest0-21swapper/221:21:194
146439934352073435200cyclictest0-21swapper/121:21:181
14175210794sleep30-21swapper/319:05:525
14323210392sleep10-21swapper/119:07:501
14296210190sleep50-21swapper/519:07:297
128501000irq/42-ahci0-21swapper/219:08:544
1448529893sleep70-21swapper/719:09:209
2014050860irq/53-eth0-rx-0-21swapper/819:08:2410
1425628572sleep60-21swapper/619:06:558
1416828273sleep100-21swapper/1019:05:462
2014050710irq/53-eth0-rx-0-21swapper/919:07:5211
1427727058sleep00-21swapper/019:07:130
1432626553sleep40-21swapper/419:07:526
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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