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2026-05-21 - 00:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot3.osadl.org (updated Wed May 20, 2026 12:46:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9919501150irq/54-eth0-tx-0-21swapper/107:07:121
22782210491sleep50-21swapper/507:06:527
991850980irq/53-eth0-rx-0-21swapper/307:06:015
991850980irq/53-eth0-rx-0-21swapper/207:07:454
2296829787sleep90-21swapper/907:08:3211
991850960irq/53-eth0-rx-0-21swapper/1107:06:463
991850940irq/53-eth0-rx-0-21swapper/407:05:066
991850920irq/53-eth0-rx-0-21swapper/1007:07:452
991950830irq/54-eth0-tx-0-21swapper/707:06:379
12850800irq/42-ahci0-21swapper/807:09:2310
2282525955sleep00-21swapper/007:07:240
2279725955sleep60-21swapper/607:07:068
991850300irq/53-eth0-rx-0-21swapper/110:27:401
23219993029cyclictest991950irq/54-eth0-tx-10:27:233
23195993029cyclictest991950irq/54-eth0-tx-10:27:326
23194993029cyclictest12850irq/42-ahci10:27:365
23218992928cyclictest991950irq/54-eth0-tx-10:27:382
23216992928cyclictest991850irq/53-eth0-rx-10:27:2610
23215992928cyclictest991950irq/54-eth0-tx-10:27:389
23217992625cyclictest15192-21ssh10:27:3011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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