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2024-04-26 - 17:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot3.osadl.org (updated Fri Apr 26, 2024 12:46:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
8602210892sleep00-21swapper/007:06:320
7515210794sleep60-21swapper/607:05:268
118501040irq/42-ahci0-21swapper/107:09:411
8453210090sleep50-21swapper/507:05:377
11850960irq/42-ahci0-21swapper/207:09:054
11850940irq/42-ahci0-21swapper/407:08:156
11850930irq/42-ahci0-21swapper/807:08:1410
2224850920irq/44-eth0-rx-0-21swapper/1007:06:092
2224950910irq/45-eth0-tx-0-21swapper/707:08:129
11850900irq/42-ahci0-21swapper/907:08:3911
11850840irq/42-ahci0-21swapper/307:05:215
2224850670irq/44-eth0-rx-0-21swapper/1107:07:213
9037994443cyclictest0-21swapper/007:23:170
906499320cyclictest0-21swapper/1107:14:403
9064992928cyclictest0-21swapper/1110:28:463
11850280irq/42-ahci0-21swapper/907:23:1611
11850280irq/42-ahci0-21swapper/807:23:2110
11850280irq/42-ahci0-21swapper/707:23:159
11850280irq/42-ahci0-21swapper/507:23:147
11850280irq/42-ahci0-21swapper/307:23:135
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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