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2025-01-18 - 15:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot3.osadl.org (updated Sat Jan 18, 2025 12:46:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20193210995sleep100-21swapper/1007:07:512
20193210995sleep100-21swapper/1007:07:512
20133210894sleep90-21swapper/907:07:0111
20133210894sleep90-21swapper/907:07:0111
20130501080irq/52-eth0-rx-0-21swapper/207:05:254
20130501080irq/52-eth0-rx-0-21swapper/207:05:254
2013050980irq/52-eth0-rx-0-21swapper/107:09:331
2013050980irq/52-eth0-rx-0-21swapper/107:09:331
12050980irq/42-ahci0-21swapper/807:09:0910
12050980irq/42-ahci0-21swapper/807:09:0810
2013150950irq/53-eth0-tx-0-21swapper/707:05:269
2013150950irq/53-eth0-tx-0-21swapper/707:05:259
2013050930irq/52-eth0-rx-0-21swapper/407:07:156
2013050930irq/52-eth0-rx-0-21swapper/407:07:146
2013150920irq/53-eth0-tx-0-21swapper/307:05:175
2013150920irq/53-eth0-tx-0-21swapper/307:05:175
2015026354sleep110-21swapper/1107:07:153
2015026354sleep110-21swapper/1107:07:153
2007726353sleep60-21swapper/607:06:228
2007726353sleep60-21swapper/607:06:228
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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