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2024-09-16 - 04:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot3.osadl.org (updated Mon Sep 16, 2024 00:46:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5945211095sleep90-21swapper/919:06:4311
11053501070irq/53-eth0-tx-0-21swapper/119:09:201
122501000irq/42-ahci0-21swapper/219:09:154
619829489sleep40-21swapper/419:09:276
1105250900irq/52-eth0-rx-0-21swapper/819:05:1410
1105250900irq/52-eth0-rx-0-21swapper/519:05:227
12250880irq/42-ahci0-21swapper/319:08:425
1105250870irq/52-eth0-rx-0-21swapper/1119:05:413
466526866sleep100-21swapper/1019:05:202
588626654sleep00-21swapper/019:05:570
592626353sleep70-21swapper/719:06:289
589326151sleep60-21swapper/619:06:048
6340994629cyclictest12525-21chrt21:27:360
638399378cyclictest126102sleep1121:28:483
638399270cyclictest0-21swapper/1121:30:163
638399270cyclictest0-21swapper/1121:16:543
634099268cyclictest0-21swapper/019:23:390
638399250cyclictest0-21swapper/1121:14:453
638299258cyclictest831ksoftirqd/1020:46:472
638299247cyclictest831ksoftirqd/1021:54:402
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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