You are here: Home / Projects / QA Farm Realtime / Latency plots / 
2022-01-22 - 15:16

Intel(R) Core(TM) i7 CPU X 980 @ 3.33GHz, Linux 3.12.31-rt45 (Profile)

Latency plot of system in rack #3, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack3slot3.osadl.org (updated Sat Jan 22, 2022 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4238501110irq/52-eth0-rx-0-21swapper/705:23:279
23303210895sleep100-21swapper/1005:20:382
4238501040irq/52-eth0-rx-0-21swapper/805:24:3210
4238501040irq/52-eth0-rx-0-21swapper/205:24:174
123501020irq/42-ahci0-21swapper/105:24:101
423850890irq/52-eth0-rx-0-21swapper/505:21:397
12350890irq/42-ahci0-21swapper/305:23:245
12350800irq/42-ahci0-21swapper/905:23:1911
111650760irq/18-i801_smb0-21swapper/405:24:146
2337926654sleep00-21swapper/005:20:400
2143226656sleep110-21swapper/1105:20:153
2432926454sleep60-21swapper/605:22:108
24745994133cyclictest0-21swapper/1107:26:193
24745993617cyclictest0-21swapper/1106:35:443
24716993515cyclictest0-21swapper/007:27:340
24716993416cyclictest0-21swapper/007:24:450
24716993416cyclictest0-21swapper/007:24:450
2471699310cyclictest0-21swapper/006:24:430
2474499236cyclictest831ksoftirqd/1008:35:152
2471699230cyclictest0-21swapper/006:25:020
2474599210cyclictest0-21swapper/1107:44:233
2474499203cyclictest831ksoftirqd/1006:59:592
2474599180cyclictest0-21swapper/1107:45:373
24744991817cyclictest831ksoftirqd/1005:55:272
24744991817cyclictest831ksoftirqd/1005:30:222
24744991817cyclictest0-21swapper/1007:10:352
2474499181cyclictest831ksoftirqd/1010:50:242
2474499181cyclictest831ksoftirqd/1010:00:102
2474499181cyclictest831ksoftirqd/1006:50:162
2474499181cyclictest831ksoftirqd/1006:25:312
2474499181cyclictest831ksoftirqd/1005:25:022
2474499181cyclictest423850irq/52-eth0-rx-10:20:282
2474499181cyclictest423850irq/52-eth0-rx-10:20:282
2474499181cyclictest423850irq/52-eth0-rx-09:14:142
2474499181cyclictest423850irq/52-eth0-rx-09:05:092
2474499181cyclictest423850irq/52-eth0-rx-08:45:262
2474499181cyclictest12350irq/42-ahci10:34:382
2474499181cyclictest12350irq/42-ahci10:34:382
2474499181cyclictest12350irq/42-ahci08:02:182
2474199185cyclictest0-21swapper/708:49:559
24741991816cyclictest9503-21snmp_rack3slot905:45:209
24741991816cyclictest9272-21snmp_easybox.os06:30:179
24741991816cyclictest4235-21snmp_easybox.os09:20:109
24741991816cyclictest3702-21snmp_easybox.os08:35:119
24741991816cyclictest31152-21perl10:40:109
24741991816cyclictest20751-21snmp_easybox.os07:30:149
24741991816cyclictest15386-21snmp_easybox.os09:35:119
24740991816cyclictest27917-21qemu-kvm08:40:138
24740991816cyclictest27917-21qemu-kvm08:30:138
24734991816cyclictest2281-21snmpd08:56:574
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional