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2021-01-28 - 12:18

Intel(R) Core(TM) i7 CPU X 980 @ 3.33GHz, Linux 3.12.31-rt45 (Profile)

Latency plot of system in rack #3, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack3slot3.osadl.org (updated Thu Jan 28, 2021 00:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31954501110irq/52-eth0-rx-0-21swapper/318:13:195
31954501110irq/52-eth0-rx-0-21swapper/318:13:195
31954501110irq/52-eth0-rx-0-21swapper/218:10:084
31954501110irq/52-eth0-rx-0-21swapper/218:10:084
28600210995sleep90-21swapper/918:12:0611
28600210995sleep90-21swapper/918:12:0611
28550210694sleep80-21swapper/818:11:2910
28550210694sleep80-21swapper/818:11:2910
28639210190sleep50-21swapper/518:12:387
28639210190sleep50-21swapper/518:12:387
3195450960irq/52-eth0-rx-0-21swapper/118:14:161
3195450960irq/52-eth0-rx-0-21swapper/118:14:161
3195450950irq/52-eth0-rx-0-21swapper/418:12:526
3195450950irq/52-eth0-rx-0-21swapper/418:12:526
2881229589sleep70-21swapper/718:14:179
2881229589sleep70-21swapper/718:14:179
3195450910irq/52-eth0-rx-0-21swapper/1118:12:293
3195450910irq/52-eth0-rx-0-21swapper/1118:12:293
2859728475sleep60-21swapper/618:12:038
2859728475sleep60-21swapper/618:12:038
2881528078sleep100-21swapper/1018:14:202
2881528078sleep100-21swapper/1018:14:202
2848225955sleep00-21swapper/018:10:330
2848225955sleep00-21swapper/018:10:330
29002993217cyclictest0-21swapper/1121:17:373
551210ksoftirqd/60-21swapper/618:15:448
551210ksoftirqd/60-21swapper/618:15:448
2899599192cyclictest3195450irq/52-eth0-rx-21:25:042
481180ksoftirqd/50-21swapper/518:16:137
481180ksoftirqd/50-21swapper/518:16:137
29002991817cyclictest3195450irq/52-eth0-rx-18:16:213
29002991817cyclictest3195450irq/52-eth0-rx-18:16:213
28995991817cyclictest0-21swapper/1023:34:552
28995991816cyclictest26280-1kworker/10:0H18:30:052
2899599181cyclictest3195450irq/52-eth0-rx-19:33:572
2899599181cyclictest12050irq/42-ahci21:13:272
2899599181cyclictest12050irq/42-ahci21:13:272
2899599181cyclictest12050irq/42-ahci19:21:182
2899599181cyclictest12050irq/42-ahci19:14:132
2899099181cyclictest761ksoftirqd/920:40:1811
2899099181cyclictest761ksoftirqd/919:55:0811
2899099181cyclictest0-21swapper/923:00:0411
2899099181cyclictest0-21swapper/922:13:0311
2899099181cyclictest0-21swapper/920:20:0211
2899099181cyclictest0-21swapper/918:20:1211
2898499184cyclictest0-21swapper/721:05:599
2898399184cyclictest0-21swapper/619:08:328
2897499180cyclictest0-21swapper/418:18:136
2897499180cyclictest0-21swapper/418:18:136
2894699182cyclictest0-21swapper/020:35:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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