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2023-01-29 - 16:20

x86 Intel Core i7-X980 @3333 MHz, Linux 3.12.31-rt45 (Profile)

Latency plot of system in rack #3, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack3slot3.osadl.org (updated Sun Jan 29, 2023 12:46:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120501130irq/42-ahci0-21swapper/207:09:284
18976211195sleep00-21swapper/007:07:530
18914210995sleep90-21swapper/907:07:0311
18842210895sleep30-21swapper/307:06:085
18964210593sleep10-21swapper/107:07:431
18927210393sleep80-21swapper/807:07:1410
18817210391sleep60-21swapper/607:05:488
12050960irq/42-ahci0-21swapper/707:09:189
1916229082sleep100-21swapper/1007:09:412
1918428075sleep40-21swapper/407:09:596
1895526755sleep50-21swapper/507:07:357
1896126253sleep110-21swapper/1107:07:413
19284993517cyclictest0-21swapper/008:28:460
19284992928cyclictest0-21swapper/009:20:520
1933199210cyclictest0-21swapper/1107:21:173
1933199190cyclictest0-21swapper/1109:27:283
1933099192cyclictest1115450irq/53-eth0-tx-08:20:182
1933099192cyclictest1115350irq/52-eth0-rx-09:08:292
19330991817cyclictest811rcuc/1011:19:432
1933099181cyclictest831ksoftirqd/1009:35:222
1933099181cyclictest12050irq/42-ahci10:08:252
1933099181cyclictest12050irq/42-ahci07:47:302
1933099181cyclictest12050irq/42-ahci07:47:292
1933099181cyclictest1115350irq/52-eth0-rx-10:30:352
1932999181cyclictest741rcuc/912:24:0211
1932999181cyclictest0-21swapper/912:38:2411
1932999181cyclictest0-21swapper/910:32:2611
1932999181cyclictest0-21swapper/909:51:2111
1932999181cyclictest0-21swapper/909:44:1511
1932999181cyclictest0-21swapper/909:39:1611
1932999181cyclictest0-21swapper/909:31:4911
1932999181cyclictest0-21swapper/909:21:2611
1932999181cyclictest0-21swapper/909:17:5711
1932999181cyclictest0-21swapper/909:12:3511
1932999181cyclictest0-21swapper/909:00:1911
1932999181cyclictest0-21swapper/908:14:1111
1932999181cyclictest0-21swapper/908:14:1111
1932999181cyclictest0-21swapper/907:45:0411
1932999181cyclictest0-21swapper/907:45:0311
1932999181cyclictest0-21swapper/907:40:3311
19323991816cyclictest31837-21qemu-kvm08:45:177
19323991816cyclictest31837-21qemu-kvm08:35:177
19323991816cyclictest31837-21qemu-kvm08:26:497
19323991816cyclictest31837-21qemu-kvm08:21:477
19323991816cyclictest31837-21qemu-kvm08:15:157
19299991816cyclictest2383-21snmpd08:38:194
19330991716cyclictest30342-21kworker/10:107:40:182
19330991716cyclictest303182sleep1011:45:592
19330991716cyclictest230372sleep1011:35:472
19330991716cyclictest0-21swapper/1008:55:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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