You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-16 - 02:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot4.osadl.org (updated Mon Feb 16, 2026 00:46:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1217309223952377,10sleep50-21swapper/519:05:405
121817699143104,31cyclictest1392408-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
23:21:270
121817699143104,31cyclictest1392408-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
23:21:260
121818599135121,7cyclictest1384422-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
22:56:242
121818599132120,6cyclictest1488616-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
00:33:392
12181769912161,31cyclictest1467750-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
00:01:350
12181769912161,31cyclictest1467750-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
00:01:350
12181769911851,46cyclictest1294787-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
21:48:000
121818199114105,6cyclictest210-21kswapd000:30:261
121819499113100,7cyclictest1269967-21diskmemload-423:21:274
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional