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2022-07-01 - 00:24

x86 VIA Nano X2 L4050 @1400 MHz, Linux 3.18.36-rt38 (Profile)

Latency plot of system in rack #3, slot #4
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot4.osadl.org (updated Fri Dec 21, 2018 12:43:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32101995938,15cyclictest15797-21date10:35:130
103832540,4sleep010384-21basename11:09:520
3210199511,5cyclictest14785-21diskstats11:14:560
3210199491,32cyclictest2311-21missed_timers07:15:110
32101994733,4cyclictest0-21swapper/010:50:120
32101994732,5cyclictest24491-21ssh09:25:410
32101994731,7cyclictest439-21runrttasks12:10:190
3210199472,29cyclictest6656-21sshd07:27:110
32101994631,5cyclictest0-21swapper/011:20:160
3210199461,29cyclictest24089-21timerwakeupswit09:25:150
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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