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2026-03-06 - 10:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack3slot4.osadl.org (updated Fri Mar 06, 2026 00:46:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28790372781767,6sleep22864337-21kworker/2:2+events@
dbs_work_handler
19:05:212
2880533991261,87cyclictest3048530-21rm22:42:370
293646321250,4sleep42932430-21diskmemload-421:16:254
288053899122108,7cyclictest2916733-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
20:42:351
288054499120106,7cyclictest3055196-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
23:02:562
288054499120106,7cyclictest3055196-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
23:02:562
288053899117104,7cyclictest3099645-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
23:38:021
2880533991172,83cyclictest0-21swapper/022:50:160
2880533991172,83cyclictest0-21swapper/022:50:160
2880533991171,48cyclictest0-21swapper/020:40:120
288054499115100,8cyclictest2923999-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
21:12:412
288054499115100,8cyclictest2923999-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
21:12:412
2880533991153,81cyclictest2980040-21aten2_r3power_f21:50:190
2880533991122,94cyclictest2891040-21aten2_r3power_f19:35:170
2880533991122,86cyclictest2928978-21diskmemload21:25:010
2880533991122,86cyclictest2928978-21diskmemload21:25:000
2880533991121,98cyclictest0-21swapper/023:30:310
2880533991121,98cyclictest0-21swapper/022:49:410
2880533991121,97cyclictest0-21swapper/021:55:370
2880533991121,89cyclictest0-21swapper/022:59:070
2880533991121,89cyclictest0-21swapper/022:59:060
28805389911197,8cyclictest3113868-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:53:351
28805339911178,14cyclictest13300-21snmpd21:10:240
28805339911178,14cyclictest13300-21snmpd21:10:240
28805339911163,22cyclictest3176007-21ntpq00:20:370
2880533991111,95cyclictest0-21swapper/019:20:290
28805339911078,23cyclictest0-21swapper/019:40:350
2880533991092,94cyclictest0-21swapper/020:50:320
2880533991091,95cyclictest0-21swapper/019:15:010
2880533991091,3cyclictest0-21swapper/023:15:110
2880533991081,93cyclictest0-21swapper/022:27:070
2880533991081,90cyclictest0-21swapper/021:00:310
2880533991081,71cyclictest0-21swapper/000:35:120
28805389910693,6cyclictest3073940-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:22:571
28805389910692,7cyclictest2931779-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
21:37:471
2880533991061,92cyclictest0-21swapper/023:14:320
2880533991061,92cyclictest0-21swapper/022:38:370
2880533991061,90cyclictest2928978-21diskmemload22:00:420
28805339910571,20cyclictest68950irq/527-eth0-Tx00:18:390
2880533991052,5cyclictest2966498-21cat21:40:010
2880533991052,40cyclictest0-21swapper/000:30:170
2880533991051,54cyclictest3019746-21awk22:20:280
28805339910459,27cyclictest2958807-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
22:07:170
28805339910459,27cyclictest2958807-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
22:07:160
2880533991042,84cyclictest0-21swapper/020:24:400
2880533991042,84cyclictest0-21swapper/020:24:390
2880533991042,55cyclictest2951271-21ssh21:28:090
2880533991042,55cyclictest2951271-21ssh21:28:080
28805389910390,6cyclictest3024515-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:27:491
28805339910371,19cyclictest0-21swapper/019:15:370
2880533991032,74cyclictest2911246-21aten2_r3power_p20:25:190
2880533991032,5cyclictest3117390-21ntpq23:35:320
2880533991021,78cyclictest0-21swapper/020:10:010
28805339910127,47cyclictest3077808-21/usr/sbin/munin23:05:200
28805339910127,47cyclictest3077808-21/usr/sbin/munin23:05:200
28805339910127,27cyclictest0-21swapper/022:10:350
2880533991011,88cyclictest0-21swapper/022:31:520
2880533991011,48cyclictest0-21swapper/000:29:090
28805449910087,6cyclictest3113868-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:56:352
2880533991001,54cyclictest0-21swapper/019:54:410
2880533991001,3cyclictest0-21swapper/021:15:440
2880533999965,20cyclictest0-21swapper/020:30:440
2880533999958,31cyclictest69150irq/529-eth0-Tx23:45:040
288053399992,87cyclictest0-21swapper/020:55:020
288053399992,52cyclictest3097349-21df_abs23:20:230
288053399991,88cyclictest0-21swapper/020:45:200
288053399991,86cyclictest0-21swapper/019:25:350
288053399991,85cyclictest0-21swapper/020:10:150
288053399991,84cyclictest0-21swapper/020:15:330
2880544999883,7cyclictest2978746-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
21:55:422
2880533999854,28cyclictest3145283-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
00:10:320
288053399982,79cyclictest3128822-21sed23:45:010
288053399981,4cyclictest3143524-21ssh23:55:410
288053399981,48cyclictest0-21swapper/020:00:370
288053399981,48cyclictest0-21swapper/020:00:370
2880538999784,6cyclictest2931779-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
21:32:451
288053399972,88cyclictest14350irq/98-imx_mu_c21:30:340
2880548999683,6cyclictest2923999-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
21:02:393
2880538999682,7cyclictest2888348-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
19:32:281
2880538999682,7cyclictest2888348-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
19:32:281
288053399962,84cyclictest0-21swapper/000:08:190
288053399961,47cyclictest0-21swapper/021:40:220
2880538999580,7cyclictest3164004-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
00:30:261
288053399956,33cyclictest3072378-21cat23:00:470
288053399956,33cyclictest3072378-21cat23:00:460
2880533999463,19cyclictest0-21swapper/019:31:490
2880533999463,19cyclictest0-21swapper/019:31:490
2880533999454,7cyclictest2895524-21sed19:45:230
2880533999454,7cyclictest2895524-21sed19:45:230
2880533999445,31cyclictest0-21swapper/021:05:380
2880533999425,27cyclictest3103848-21df_abs23:25:220
288053399941,49cyclictest0-21swapper/021:49:230
2880533999354,20cyclictest2928978-21diskmemload00:00:350
2880533999344,29cyclictest0-21swapper/020:38:360
2880533999344,29cyclictest0-21swapper/020:38:360
288053399931,83cyclictest48-21rcuop/423:55:010
2880538999176,8cyclictest3048081-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
22:50:121
2880538999176,8cyclictest3048081-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
22:50:111
2880548999076,7cyclictest2926658-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
21:06:333
2880538999068,8cyclictest2931779-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
22:09:441
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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