You are here: Home / Projects / QA Farm Realtime / Latency plots / 
2019-07-24 - 00:31

VIA Nano X2 L4050 @ 1.4 GHz, Linux 3.18.36-rt38 (Profile)

Latency plot of system in rack #3, slot #4
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot4.osadl.org (updated Fri Dec 21, 2018 12:43:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32101995938,15cyclictest15797-21date10:35:130
103832540,4sleep010384-21basename11:09:520
3210199511,5cyclictest14785-21diskstats11:14:560
3210199491,32cyclictest2311-21missed_timers07:15:110
32101994733,4cyclictest0-21swapper/010:50:120
32101994732,5cyclictest24491-21ssh09:25:410
32101994731,7cyclictest439-21runrttasks12:10:190
3210199472,29cyclictest6656-21sshd07:27:110
32101994631,5cyclictest0-21swapper/011:20:160
3210199461,29cyclictest24089-21timerwakeupswit09:25:150
3210199458,32cyclictest37150irq/33-eth010:54:470
3210199452,6cyclictest18867-21missed_timers12:40:030
32101994431,4cyclictest0-21swapper/007:55:230
32101994429,5cyclictest5974-21latency08:55:080
32101994424,5cyclictest0-21swapper/010:25:040
3210199442,37cyclictest4809-21ssh11:42:210
3210199441,6cyclictest20029-21timerandwakeup09:20:150
3210199441,4cyclictest0-21swapper/007:40:040
3210199441,39cyclictest0-21swapper/008:10:170
3210199441,28cyclictest4172-21latency08:50:080
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional