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2026-01-15 - 06:35
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot4.osadl.org (updated Thu Jan 15, 2026 00:46:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4037908235113493,6sleep24018778-21kworker/2:2+events@
dbs_work_handler
19:08:152
40382089914637,90cyclictest4080539-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
20:55:290
40382089913942,81cyclictest48175-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
23:20:050
40382089913942,81cyclictest48175-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
23:20:040
40382089913328,62cyclictest4084548-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
21:17:180
40382089912737,79cyclictest4052364-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
19:45:150
40382089912452,53cyclictest73774-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
00:07:270
40382089912372,31cyclictest4066246-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
20:53:050
403821299118105,6cyclictest4084702-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
21:50:341
403821699113101,6cyclictest4038199-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
19:45:092
40382089911261,43cyclictest35876-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
23:10:300
404541321110,5sleep10-21swapper/119:25:351
404541321110,5sleep10-21swapper/119:25:341
4038208991101,81cyclictest0-21swapper/020:40:490
40382129910994,8cyclictest4084702-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
21:35:321
40382269910699,3cyclictest0-21swapper/422:30:414
40382269910598,3cyclictest0-21swapper/400:28:384
40382169910492,6cyclictest24273-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
23:32:362
40382219910362,9cyclictest67356-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
23:43:253
40382169910088,6cyclictest4163233-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:15:392
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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