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2026-05-16 - 19:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot4.osadl.org (updated Sat May 16, 2026 12:46:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3917847226112571,26sleep03898038-21kworker/0:1+events@
dbs_work_handler
07:05:280
39187532868857,6sleep50-21swapper/507:08:485
39190109914072,49cyclictest4030554-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
10:55:240
391901099135112,15cyclictest10577-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
12:31:090
391901999123111,6cyclictest3995681-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
09:45:462
39190109912278,28cyclictest4188255-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
12:10:550
39190109912278,28cyclictest4188255-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
12:10:550
39190109912060,52cyclictest4016363-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
09:50:190
391901599119104,8cyclictest3987470-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
10:00:481
391901599119104,8cyclictest3987470-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
10:00:481
39190109911985,27cyclictest4188255-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
12:36:120
39190109911930,45cyclictest0-21swapper/010:30:390
39190249911787,10cyclictest3978874-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
09:25:313
39190249911787,10cyclictest3978874-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
09:25:313
396905421160,8sleep336-21rcuc/309:10:413
39190159911298,7cyclictest4009729-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
09:55:461
39190199911098,6cyclictest3987470-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
09:27:342
39190199911098,6cyclictest3987470-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
09:27:342
39190159911086,9cyclictest4055475-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
10:24:041
39190159911071,8cyclictest4158478-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
11:53:341
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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