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2026-06-17 - 11:53
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OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of system in rack #3, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack3slot4.osadl.org (updated Wed Jun 17, 2026 00:46:19)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)		T*(,W**)
latency
(µs)		CmdPIDPrioCmd
7743889912867,49cyclictest67350irq/527-eth0-Tx21:10:350
108599221020,3sleep50-21swapper/500:25:375
774388999958,18cyclictest67350irq/527-eth0-Tx21:25:120
8255882980,4sleep50-21swapper/521:12:015
77438899972,64cyclictest0-21swapper/019:15:010
774388999649,19cyclictest1019435-21ps23:35:390
77438899952,61cyclictest0-21swapper/020:35:430
774388999360,17cyclictest792284-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork		20:11:100
774388999355,15cyclictest67450irq/528-eth0-Tx20:55:210
774388999255,16cyclictest0-21swapper/020:50:150
77438899911,76cyclictest0-21swapper/021:39:040
774388999051,4cyclictest67350irq/527-eth0-Tx22:15:320
774388998841,4cyclictest67650irq/530-eth0-Tx22:45:130
774388998226,26cyclictest67350irq/527-eth0-Tx22:50:220
774388998164,4cyclictest0-21swapper/023:56:130
77438899811,66cyclictest0-21swapper/019:52:130
77438899811,66cyclictest0-21swapper/019:52:130
77438899802,65cyclictest0-21swapper/021:20:010
774398997965,7cyclictest984948-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork		23:11:482
774388997911,52cyclictest13-21ksoftirqd/000:15:210
774388997911,52cyclictest13-21ksoftirqd/000:15:210
774388997651,14cyclictest67350irq/527-eth0-Tx23:15:370
774407997570,2cyclictest0-21swapper/419:56:074
774388997542,17cyclictest67350irq/527-eth0-Tx23:25:330
774388997465,4cyclictest0-21swapper/022:05:450
774388997444,21cyclictest67350irq/527-eth0-Tx00:20:230
774388997439,4cyclictest0-21swapper/019:25:130
77438899742,5cyclictest855135-21latency_hist21:35:000
77438899742,55cyclictest15-21rcuc/022:35:430
774407997368,2cyclictest0-21swapper/419:25:154
774402997362,5cyclictest948746-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork		23:01:463
774388997351,8cyclictest1018204-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork		23:45:350
774402997258,7cyclictest1040457-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork		00:12:033
774388997260,8cyclictest802471-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork		20:21:130
774388997260,8cyclictest802471-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork		20:21:130
774388997233,3cyclictest0-21swapper/022:04:410
774388997233,3cyclictest0-21swapper/022:04:400
77438899722,53cyclictest1064790-21acpi00:10:100
774402997157,7cyclictest878850-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork		21:55:463
774407996963,3cyclictest0-21swapper/421:13:124
774398996955,7cyclictest1002548-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork		23:26:512
774398996953,8cyclictest778167-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork		19:21:002
774388996944,14cyclictest0-21swapper/020:25:150
774388996933,18cyclictest0-21swapper/000:03:310
774388996931,16cyclictest67650irq/530-eth0-Tx00:32:210
774388996926,17cyclictest13-21ksoftirqd/022:35:020
77438899691,25cyclictest0-21swapper/000:05:230
774407996862,3cyclictest0-21swapper/419:36:274
774407996862,3cyclictest0-21swapper/419:36:274
774402996854,7cyclictest822643-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork		21:26:263
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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