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2026-02-11 - 01:06
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of system in rack #3, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack3slot4.osadl.org (updated Tue Feb 10, 2026 12:46:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)		T*(,W**)
latency
(µs)		CmdPIDPrioCmd
568388213631343,9sleep2563591-21kworker/2:0+events@
dbs_work_handler		07:05:192
5681212885857,9sleep1561392-21kworker/1:1+events@
dbs_work_handler		07:05:101
5699919913429,57cyclictest606828-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork		11:30:390
57000099130117,6cyclictest799645-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork		11:39:512
5699919912675,41cyclictest68950irq/527-eth0-Tx12:05:380
569991991241,64cyclictest0-21swapper/009:57:090
5699919912269,36cyclictest569506-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork		07:13:380
5699919912260,54cyclictest799645-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork		11:47:440
5699919912253,35cyclictest0-21swapper/008:50:230
569991991202,90cyclictest0-21swapper/007:25:170
5699919911975,21cyclictest68950irq/527-eth0-Tx11:10:210
5699919911476,4cyclictest68950irq/527-eth0-Tx09:00:340
5700009911399,7cyclictest817638-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork		12:14:572
5700009911399,7cyclictest606828-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork		09:29:312
5699919911375,7cyclictest68950irq/527-eth0-Tx07:40:240
5699919911367,15cyclictest68950irq/527-eth0-Tx10:40:190
5699919911367,15cyclictest68950irq/527-eth0-Tx10:40:190
5699919911169,12cyclictest68950irq/527-eth0-Tx10:03:270
5699919910760,13cyclictest635230-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork		09:48:170
5700009910690,8cyclictest587823-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork		08:04:092
5700009910591,7cyclictest678393-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork		10:04:392
5699919910571,7cyclictest571775-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork		07:30:280
5699919910555,29cyclictest606828-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork		11:05:100
5700009910492,6cyclictest635230-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork		09:34:362
5699919910378,4cyclictest69250irq/530-eth0-Tx08:30:310
5699919910271,5cyclictest591242-21ntpq08:00:330
5700009910189,6cyclictest606828-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork		09:54:382
5699919910168,3cyclictest0-21swapper/010:35:350
5699919910165,15cyclictest69150irq/529-eth0-Tx12:35:380
5699919910165,13cyclictest69050irq/528-eth0-Tx12:25:300
570000999987,6cyclictest606828-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork		09:09:242
570000999886,6cyclictest696660-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork		11:24:492
570000999885,7cyclictest622528-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork		09:23:352
569991999871,16cyclictest68950irq/527-eth0-Tx10:45:150
569991999871,16cyclictest68950irq/527-eth0-Tx10:45:150
570000999767,7cyclictest750633-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork		11:05:412
570000999682,7cyclictest592646-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork		08:20:432
570009999589,3cyclictest0-21swapper/410:54:464
570000999566,6cyclictest799645-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork		12:15:342
570000999480,7cyclictest645055-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork		10:11:332
570000999480,7cyclictest635230-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork		09:49:372
570000999468,7cyclictest606828-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork		10:09:002
570000999380,6cyclictest606828-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork		09:39:342
569991999367,14cyclictest69050irq/528-eth0-Tx10:15:230
569991999367,14cyclictest69050irq/528-eth0-Tx10:15:230
570000999280,6cyclictest569506-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork		07:20:342
570000999280,6cyclictest569506-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork		07:20:332
569991999270,5cyclictest0-21swapper/012:00:360
569991999255,19cyclictest855016-21ssh12:17:240
56999199921,81cyclictest0-21swapper/009:10:380
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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