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2025-06-13 - 18:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack3slot4.osadl.org (updated Fri Jun 13, 2025 12:46:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1844088234423415,8sleep21839070-21kworker/2:1+events@
dbs_work_handler
07:05:202
1844503223132288,16sleep40-21swapper/407:05:274
184563499143115,10cyclictest2078251-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
12:06:561
184563499133119,7cyclictest1855362-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
07:39:531
184563499128100,9cyclictest1889820-21kworker/u12:4+events_unbound@
flush_memcg_stats_dwork
09:15:101
184565399119113,2cyclictest0-21swapper/507:14:525
18456349911398,8cyclictest2078251-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
11:46:541
18456399911297,8cyclictest1898748-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
10:15:232
18456309910883,6cyclictest2103202-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
12:21:580
18456309910883,6cyclictest2103202-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
12:21:580
18456399910794,6cyclictest1859344-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
07:54:582
18456399910685,9cyclictest2009106-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
11:11:472
18456399910490,7cyclictest1849446-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
07:29:522
20475472990,16sleep013-21ksoftirqd/011:23:400
1845639999581,7cyclictest1853339-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
07:49:572
1845644999480,7cyclictest1879463-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
08:40:073
1845649999386,3cyclictest0-21swapper/410:26:404
1845653998982,3cyclictest0-21swapper/510:26:405
184563099892,41cyclictest2139719-21ssh12:33:540
1845634998777,7cyclictest210-21kswapd010:10:211
1845634998777,7cyclictest210-21kswapd010:10:211
1845653998669,11cyclictest2121776-21chrt12:20:195
1845653998669,11cyclictest2121776-21chrt12:20:195
1845630998537,36cyclictest64250irq/527-eth0-Tx07:30:370
184563099851,3cyclictest0-21swapper/011:55:350
1845630998468,7cyclictest1971166-21kworker/u12:5+events_unbound@
flush_memcg_stats_dwork
10:21:040
1845653998376,3cyclictest0-21swapper/512:31:585
1845634998368,8cyclictest1898748-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
10:21:531
1845630998227,11cyclictest1895230-21grep09:10:410
1845630998227,11cyclictest1895230-21grep09:10:410
184563099821,53cyclictest0-21swapper/007:44:450
184563099821,53cyclictest0-21swapper/007:44:450
1845634998168,6cyclictest2009106-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
11:06:451
1845630998166,8cyclictest2085924-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
12:00:240
1845630998166,8cyclictest2085924-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
12:00:230
1845639997964,7cyclictest1898748-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
09:40:162
1845630997921,3cyclictest0-21swapper/009:51:460
1845653997871,3cyclictest0-21swapper/510:55:485
1845639997863,7cyclictest1994467-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
10:56:462
1845639997862,8cyclictest2035751-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
11:31:522
1845639997862,8cyclictest2035751-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
11:31:512
1845634997865,7cyclictest1865275-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
08:41:571
1845630997835,6cyclictest64250irq/527-eth0-Tx11:25:250
1845634997765,6cyclictest2061403-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
11:51:551
1845634997765,6cyclictest2061403-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
11:51:541
184563099778,5cyclictest64550irq/530-eth0-Tx10:35:230
1845630997740,5cyclictest64250irq/527-eth0-Tx11:00:370
184563099771,4cyclictest14250irq/98-imx_mu_c10:09:160
1845653997670,3cyclictest0-21swapper/508:55:395
1845653997670,3cyclictest0-21swapper/508:55:395
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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