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2019-07-24 - 00:37

Intel(R) Atom(TM) CPU N455 @ 1.66GHz, Linux 3.18.36-rt38 (Profile)

Latency plot of system in rack #3, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot6.osadl.org (updated Sat Jul 16, 2016 00:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
87299912527cyclictest27853-21ld00:13:121
8729991145cyclictest0-21swapper/119:22:111
8729991144cyclictest10089-21cc120:05:221
8729991123cyclictest27616-21make22:13:051
8729991116cyclictest10483-21cc122:34:351
87299911016cyclictest21282-21gcc19:30:261
8729991095cyclictest0-21swapper/119:41:041
8729991094cyclictest7195-21kworker/u4:200:02:161
8729991085cyclictest0-21swapper/120:11:401
8729991084cyclictest23380-21make22:06:171
8729991075cyclictest30424-21mv23:00:371
8729991073cyclictest7195-21kworker/u4:222:28:301
87299910714cyclictest18748-21cc122:45:381
8729991063cyclictest18035-21cc121:11:451
87299910513cyclictest1606-21cc123:06:581
8729991045cyclictest21894-21cc100:07:331
8729991034cyclictest15478-21ssh23:27:131
87299910213cyclictest4284-21cc121:37:471
8729991006cyclictest2991-21cc122:25:201
87299910011cyclictest31183-21kworker/u4:020:00:091
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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