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2023-06-10 - 09:23

x86 Intel N455 @1660 MHz, Linux 5.15.49-rt47 (Profile)

Latency plot of system in rack #3, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack3slot6 (updated Sat Jun 10, 2023 00:45:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5007220266,89sleep10-21swapper/119:05:151
66339914072,21cyclictest14-21ksoftirqd/019:25:290
66339913780,18cyclictest14-21ksoftirqd/000:05:220
66379912685,29cyclictest26-21ksoftirqd/122:05:161
66379912530,81cyclictest0-21swapper/123:35:181
66339912421,47cyclictest14-21ksoftirqd/022:50:210
66379912120,86cyclictest0-21swapper/119:35:181
66339912190,20cyclictest14-21ksoftirqd/023:15:170
66379912075,33cyclictest26-21ksoftirqd/122:35:221
66379911813,89cyclictest0-21swapper/123:55:231
66379911811,93cyclictest0-21swapper/123:00:211
66339911889,16cyclictest14-21ksoftirqd/023:25:190
66339911887,19cyclictest14-21ksoftirqd/019:55:190
66339911851,23cyclictest14-21ksoftirqd/000:00:220
66379911713,84cyclictest0-21swapper/121:40:181
66379911669,35cyclictest26-21ksoftirqd/120:25:191
66379911667,37cyclictest26-21ksoftirqd/123:10:211
66379911667,37cyclictest26-21ksoftirqd/123:10:211
66379911615,83cyclictest0-21swapper/123:15:151
66339911686,20cyclictest0-21swapper/020:20:180
66339911683,21cyclictest14-21ksoftirqd/022:30:180
66339911631,28cyclictest0-21swapper/022:40:240
66379911514,84cyclictest0-21swapper/121:20:171
66379911514,82cyclictest0-21swapper/122:15:181
66379911513,85cyclictest0-21swapper/122:25:231
66379911513,83cyclictest0-21swapper/120:35:171
66339911586,18cyclictest14-21ksoftirqd/021:10:180
66379911414,84cyclictest0-21swapper/122:55:271
66379911412,80cyclictest0-21swapper/100:25:231
66339911486,18cyclictest14-21ksoftirqd/021:50:210
66339911484,19cyclictest14-21ksoftirqd/019:15:230
66339911484,18cyclictest14-21ksoftirqd/022:10:200
66339911484,18cyclictest14-21ksoftirqd/000:35:230
6633991147,17cyclictest0-21swapper/020:40:260
66339911448,20cyclictest7316-21avahi-daemon23:05:240
66379911320,71cyclictest0-21swapper/122:45:181
66379911314,78cyclictest0-21swapper/123:50:221
66379911312,81cyclictest0-21swapper/119:50:151
66339911384,17cyclictest14-21ksoftirqd/000:10:190
66379911217,76cyclictest0-21swapper/122:00:241
66379911214,75cyclictest0-21swapper/120:50:221
66379911213,78cyclictest0-21swapper/123:45:171
66379911213,77cyclictest0-21swapper/123:25:221
66379911213,75cyclictest0-21swapper/120:55:241
66379911149,49cyclictest26-21ksoftirqd/121:15:161
66379911149,49cyclictest26-21ksoftirqd/121:15:161
66379911114,76cyclictest0-21swapper/120:30:181
66379911113,75cyclictest0-21swapper/122:10:171
66379911113,75cyclictest0-21swapper/120:05:161
66379911110,76cyclictest0-21swapper/123:20:261
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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