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2024-11-05 - 07:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack3slot6.osadl.org (updated Tue Nov 05, 2024 00:45:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
33589913434,88cyclictest550-21snmpd20:31:190
33589911812,92cyclictest0-21swapper/023:50:130
33589911774,29cyclictest14-21ksoftirqd/022:35:130
33589911774,29cyclictest14-21ksoftirqd/022:35:130
33589911610,90cyclictest0-21swapper/021:25:140
33589911578,25cyclictest14-21ksoftirqd/000:30:140
33589911473,30cyclictest14-21ksoftirqd/022:30:160
33619911313,85cyclictest0-21swapper/122:05:111
33589911371,31cyclictest14-21ksoftirqd/020:35:160
33589911261,36cyclictest14-21ksoftirqd/021:40:140
33589911212,86cyclictest0-21swapper/020:55:110
33589911174,25cyclictest14-21ksoftirqd/021:50:150
33589911166,33cyclictest14-21ksoftirqd/019:25:130
33589911010,86cyclictest0-21swapper/021:15:130
33619910914,79cyclictest0-21swapper/122:55:161
33619910914,79cyclictest0-21swapper/122:55:151
33589910960,37cyclictest14-21ksoftirqd/020:25:140
33589910912,29cyclictest0-21swapper/020:10:130
33619910815,33cyclictest0-21swapper/121:25:131
33589910868,30cyclictest0-21swapper/020:00:140
33589910756,38cyclictest14-21ksoftirqd/021:05:120
33589910466,28cyclictest14-21ksoftirqd/023:10:110
33589910460,30cyclictest14-21ksoftirqd/022:05:120
33589910447,46cyclictest14-21ksoftirqd/021:55:160
33589910354,36cyclictest0-21swapper/019:20:140
33589910352,36cyclictest14-21ksoftirqd/021:10:160
33589910352,36cyclictest14-21ksoftirqd/021:10:150
33589910352,33cyclictest14-21ksoftirqd/021:30:120
33589910350,36cyclictest14-21ksoftirqd/022:40:120
33589910250,42cyclictest14-21ksoftirqd/022:55:130
33589910250,42cyclictest14-21ksoftirqd/022:55:120
33589910121,65cyclictest0-21swapper/023:00:120
33589910121,65cyclictest0-21swapper/023:00:110
33589910112,71cyclictest0-21swapper/023:40:130
33589910023,54cyclictest0-21swapper/021:20:130
3358999949,34cyclictest14-21ksoftirqd/000:10:150
3358999949,34cyclictest14-21ksoftirqd/000:10:140
3358999912,66cyclictest0-21swapper/020:40:120
3358999820,64cyclictest14-21ksoftirqd/019:45:140
3358999813,66cyclictest0-21swapper/023:35:140
3358999813,65cyclictest0-21swapper/022:00:130
3358999811,66cyclictest0-21swapper/020:05:110
3358999810,64cyclictest0-21swapper/023:25:130
3358999737,40cyclictest7303-21kworker/0:000:05:140
3358999718,54cyclictest0-21swapper/021:45:130
3358999713,62cyclictest0-21swapper/000:15:150
3358999712,64cyclictest0-21swapper/019:50:250
3358999712,62cyclictest0-21swapper/022:50:180
3358999644,31cyclictest14-21ksoftirqd/019:40:130
3358999620,54cyclictest0-21swapper/022:10:100
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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