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2021-09-27 - 06:32

Intel(R) Xeon(R) CPU E3-1220L V2 @ 2.30GHz, Linux 4.19.8-rt6 (Profile)

Latency plot of system in rack #4, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack4slot0.osadl.org (updated Mon Sep 27, 2021 00:44:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18362990,2sleep23204799cyclictest23:48:012
275642780,0sleep00-21swapper/021:46:450
9482730,0sleep10-21swapper/122:39:481
59172730,0sleep10-21swapper/121:40:571
145442730,1sleep20-21swapper/221:26:142
214862720,0sleep10-21swapper/121:11:041
214862720,0sleep10-21swapper/121:11:041
47092710,0sleep30-21swapper/319:20:203
280682710,2sleep23204799cyclictest23:03:492
285402690,0sleep30-21swapper/321:38:353
169962680,0sleep10-21swapper/121:35:241
297902620,2sleep13204699cyclictest22:30:141
159372620,0sleep10-21swapper/100:17:371
3151525122,8sleep10-21swapper/119:06:511
314752490,1sleep031476-21bash21:39:230
3189124428,9sleep20-21swapper/219:09:582
3177324427,10sleep00-21swapper/019:09:120
3153024325,11sleep30-21swapper/319:06:583
178562270,0sleep20-21swapper/221:35:332
191772260,0sleep20-21swapper/222:44:332
3204899250,2cyclictest0-21swapper/323:22:513
3204699240,1cyclictest0-21swapper/120:50:361
3204899233,2cyclictest0-21swapper/320:22:203
3204899233,2cyclictest0-21swapper/319:56:133
3204699233,2cyclictest0-21swapper/123:42:411
233872230,0sleep20-21swapper/222:11:112
103702230,0sleep30-21swapper/300:33:343
3204899222,2cyclictest0-21swapper/319:19:153
3204799220,4cyclictest0-21swapper/220:45:242
3204799220,4cyclictest0-21swapper/220:15:382
3204699220,4cyclictest0-21swapper/122:29:411
3204899212,2cyclictest0-21swapper/320:00:073
3204899212,1cyclictest0-21swapper/322:26:203
3204899211,2cyclictest10079-21lspci23:15:523
3204899211,2cyclictest0-21swapper/323:44:593
3204899211,2cyclictest0-21swapper/323:31:583
3204899211,2cyclictest0-21swapper/322:23:443
3204899211,2cyclictest0-21swapper/319:26:453
3204899210,2cyclictest0-21swapper/321:10:273
3204899210,2cyclictest0-21swapper/321:10:263
3204799212,1cyclictest0-21swapper/222:54:332
3204799211,2cyclictest0-21swapper/223:25:042
3204799211,2cyclictest0-21swapper/222:32:472
3204799211,2cyclictest0-21swapper/221:47:372
3204799211,2cyclictest0-21swapper/220:34:232
3204799210,4cyclictest9505-21lspci23:32:492
3204699212,2cyclictest0-21swapper/119:38:211
3204699211,1cyclictest0-21swapper/122:20:161
3204699210,3cyclictest0-21swapper/120:28:591
3204699210,3cyclictest0-21swapper/119:20:421
3204699210,3cyclictest0-21swapper/119:17:381
3204899203,2cyclictest0-21swapper/323:45:163
3204899203,2cyclictest0-21swapper/322:50:273
3204899203,2cyclictest0-21swapper/320:44:113
3204899202,2cyclictest0-21swapper/322:16:353
3204899202,2cyclictest0-21swapper/321:06:393
3204899201,2cyclictest891-21dbus-daemon20:50:003
3204899200,3cyclictest0-21swapper/319:38:403
3204899200,2cyclictest0-21swapper/321:50:433
3204899200,2cyclictest0-21swapper/320:56:093
3204899200,2cyclictest0-21swapper/319:12:563
3204799203,2cyclictest0-21swapper/220:38:442
3204799202,2cyclictest28060-21sshd00:20:452
3204799202,2cyclictest0-21swapper/223:39:552
3204799202,0cyclictest0-21swapper/222:02:362
3204799201,1cyclictest0-21swapper/220:42:052
3204799201,1cyclictest0-21swapper/219:52:162
3204799200,2cyclictest0-21swapper/220:00:522
3204799200,2cyclictest0-21swapper/219:14:102
3204799200,2cyclictest0-21swapper/200:03:372
3204799200,0cyclictest0-21swapper/222:35:172
32046992013,2cyclictest241ktimersoftd/120:22:411
3204699200,3cyclictest0-21swapper/119:46:211
3204699200,2cyclictest12916-21sshd23:16:401
3204699200,2cyclictest0-21swapper/123:48:191
3204699200,2cyclictest0-21swapper/122:56:481
3204699200,2cyclictest0-21swapper/122:46:511
3204699200,2cyclictest0-21swapper/122:13:381
3204699200,2cyclictest0-21swapper/121:32:521
3204699200,2cyclictest0-21swapper/120:15:341
104532200,1sleep0111rcuc/022:50:280
3204899192,3cyclictest8553-21sshd21:58:553
3204899192,2cyclictest25431-21sshd00:11:243
3204899190,1cyclictest0-21swapper/323:02:003
3204899190,1cyclictest0-21swapper/322:55:213
3204899190,1cyclictest0-21swapper/322:47:093
3204899190,1cyclictest0-21swapper/321:04:033
3204899190,1cyclictest0-21swapper/320:32:293
3204899190,1cyclictest0-21swapper/320:08:063
3204899190,1cyclictest0-21swapper/300:06:543
3204799194,2cyclictest0-21swapper/200:10:282
3204799190,2cyclictest0-21swapper/220:10:462
3204799190,1cyclictest0-21swapper/223:56:322
3204799190,1cyclictest0-21swapper/223:11:012
3204799190,1cyclictest0-21swapper/223:08:062
3204799190,1cyclictest0-21swapper/222:57:482
3204799190,1cyclictest0-21swapper/222:23:142
3204799190,1cyclictest0-21swapper/222:06:292
3204799190,1cyclictest0-21swapper/221:42:522
3204799190,1cyclictest0-21swapper/221:20:162
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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