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2021-06-17 - 19:52

Intel(R) Xeon(R) CPU E3-1220L V2 @ 2.30GHz, Linux 4.19.8-rt6 (Profile)

Latency plot of system in rack #4, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack4slot0.osadl.org (updated Thu Jun 17, 2021 12:44:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1052221720,3sleep22272699cyclictest10:22:342
100422730,1sleep2321ktimersoftd/210:31:062
203612700,1sleep320363-21bash10:51:273
194572700,1sleep019454-21sshd12:01:130
321262670,0sleep30-21swapper/312:39:433
307952670,0sleep20-21swapper/211:46:532
154142600,2sleep32273599cyclictest10:41:223
2253825625,10sleep10-21swapper/107:09:171
2230025226,19sleep30-21swapper/307:06:543
2259224428,9sleep20-21swapper/207:09:542
2246024427,10sleep00-21swapper/007:08:310
43902270,1sleep1241ktimersoftd/110:29:501
2272199270,3cyclictest0-21swapper/111:35:191
306722240,0sleep30-21swapper/311:46:503
6012230,0sleep20-21swapper/210:20:002
298552230,0sleep20-21swapper/210:27:512
252042230,3sleep02272099cyclictest10:26:280
2273599232,2cyclictest0-21swapper/309:50:193
2272699233,2cyclictest0-21swapper/207:50:252
2272699230,2cyclictest0-21swapper/212:39:432
145852230,1sleep11433-21nfsd10:41:081
2273599222,2cyclictest0-21swapper/310:36:473
2273599222,2cyclictest0-21swapper/307:38:333
2273599220,1cyclictest0-21swapper/310:33:493
2272699220,4cyclictest0-21swapper/210:41:272
2272699220,4cyclictest0-21swapper/208:18:562
2272699220,4cyclictest0-21swapper/207:57:562
2272699220,2cyclictest0-21swapper/209:10:332
2272199225,2cyclictest2008-21sshd10:55:251
2272199223,1cyclictest0-21swapper/111:58:241
2272199222,2cyclictest0-21swapper/108:49:411
2272199220,4cyclictest0-21swapper/109:57:261
2272199220,4cyclictest0-21swapper/108:29:521
21442220,0sleep20-21swapper/208:55:192
110492220,2sleep22272699cyclictest11:59:102
2273599212,1cyclictest891-21dbus-daemon11:30:003
2273599211,2cyclictest0-21swapper/310:55:513
2273599211,2cyclictest0-21swapper/310:27:033
2273599211,2cyclictest0-21swapper/308:58:033
2273599211,2cyclictest0-21swapper/308:10:173
2273599211,2cyclictest0-21swapper/307:21:483
2272699212,4cyclictest0-21swapper/209:58:262
2272699212,1cyclictest0-21swapper/207:15:592
2272699210,3cyclictest0-21swapper/212:17:182
2272699210,3cyclictest0-21swapper/210:03:252
2272199212,1cyclictest0-21swapper/109:30:151
2272199212,1cyclictest0-21swapper/109:30:141
2272199210,3cyclictest18216-21lspci10:33:301
2272199210,3cyclictest0-21swapper/111:41:171
2272199210,3cyclictest0-21swapper/110:05:111
2272199210,3cyclictest0-21swapper/109:24:491
2272099212,2cyclictest0-21swapper/007:11:480
2272099211,2cyclictest0-21swapper/012:15:450
2272099211,2cyclictest0-21swapper/011:27:260
2272099211,2cyclictest0-21swapper/009:10:230
2272099210,6cyclictest0-21swapper/010:20:180
2272099210,3cyclictest0-21swapper/012:23:300
2272099210,3cyclictest0-21swapper/011:52:230
2272099210,3cyclictest0-21swapper/009:53:230
2272099210,3cyclictest0-21swapper/009:40:420
2272099210,3cyclictest0-21swapper/009:38:120
2272099210,1cyclictest0-21swapper/011:49:050
205832210,0sleep30-21swapper/311:09:193
164042210,0sleep00-21swapper/009:49:060
2273599201,1cyclictest0-21swapper/311:50:123
2273599200,2cyclictest1773-21lspci11:04:133
2273599200,0cyclictest0-21swapper/308:36:523
2272699202,2cyclictest0-21swapper/212:04:312
2272699200,2cyclictest0-21swapper/210:55:272
2272699200,2cyclictest0-21swapper/208:25:232
2272699200,2cyclictest0-21swapper/208:10:122
2272199201,1cyclictest0-21swapper/109:43:461
2272199200,2cyclictest0-21swapper/112:34:161
2272199200,2cyclictest0-21swapper/112:18:001
2272199200,2cyclictest0-21swapper/110:36:151
2272199200,2cyclictest0-21swapper/110:03:371
2272099202,2cyclictest0-21swapper/008:10:450
2272099201,1cyclictest0-21swapper/008:21:320
2272099200,4cyclictest27377-21idleruntime-cro08:40:000
2272099200,2cyclictest0-21swapper/009:57:310
2272099200,2cyclictest0-21swapper/007:46:250
2273599192,2cyclictest0-21swapper/311:36:293
2273599192,2cyclictest0-21swapper/307:42:253
2273599191,2cyclictest0-21swapper/308:04:543
2273599190,2cyclictest1432-21nfsd09:56:123
2273599190,1cyclictest18641-21sshd10:24:563
2273599190,1cyclictest0-21swapper/312:29:163
2273599190,1cyclictest0-21swapper/312:16:213
2273599190,1cyclictest0-21swapper/311:32:563
2273599190,1cyclictest0-21swapper/311:15:083
2273599190,1cyclictest0-21swapper/311:14:063
2273599190,1cyclictest0-21swapper/310:17:503
2273599190,1cyclictest0-21swapper/309:14:283
2273599190,1cyclictest0-21swapper/309:02:513
2273599190,1cyclictest0-21swapper/308:52:383
2273599190,1cyclictest0-21swapper/308:46:243
2273599190,1cyclictest0-21swapper/308:44:203
2273599190,1cyclictest0-21swapper/308:16:503
2273599190,1cyclictest0-21swapper/307:32:503
2273599190,1cyclictest0-21swapper/307:19:263
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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