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2024-12-10 - 22:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack4slot0.osadl.org (updated Fri Aug 05, 2022 12:44:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1426421320,2sleep0568099cyclictest09:30:420
1077121270,0sleep010770-21sshd10:48:020
980421210,0sleep20-21swapper/211:42:552
651021160,0sleep26511-21sshd12:04:352
2941821110,2sleep2568299cyclictest11:52:242
180342930,1sleep21278-21runrttasks10:30:322
200462860,2sleep1568199cyclictest09:57:451
130462830,0sleep30-21swapper/310:15:223
42612790,0sleep30-21swapper/310:54:383
252902770,1sleep325289-21sshd11:55:343
5680997673,2cyclictest24124-21ipmitool12:10:170
299352760,0sleep10-21swapper/111:45:141
151332750,0sleep30-21swapper/310:26:363
146512750,0sleep00-21swapper/010:52:060
303372730,0sleep10-21swapper/109:51:271
230312720,1sleep1231rcuc/109:28:061
3452710,0sleep0111rcuc/012:22:160
89112700,0sleep10-21swapper/110:58:491
76242690,0sleep20-21swapper/209:56:172
176122690,0sleep10-21swapper/110:01:091
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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