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2021-10-24 - 02:04

Intel(R) Xeon(R) CPU E3-1220L V2 @ 2.30GHz, Linux 4.19.8-rt6 (Profile)

Latency plot of system in rack #4, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack4slot0.osadl.org (updated Sun Oct 24, 2021 00:44:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
429721700,0sleep10-21swapper/100:10:551
127502780,0sleep20-21swapper/221:12:132
43722770,0sleep20-21swapper/223:19:192
242752740,0sleep20-21swapper/223:59:102
93532720,2sleep11908999cyclictest00:29:471
219352720,0sleep30-21swapper/322:49:313
88632690,2sleep01908499cyclictest00:03:450
288262660,0sleep20-21swapper/223:25:442
255212650,0sleep00-21swapper/023:07:350
258352640,0sleep10-21swapper/123:50:481
64792560,0sleep30-21swapper/323:28:343
1875725127,17sleep00-21swapper/019:07:520
1885724630,9sleep30-21swapper/319:09:023
1873824427,10sleep10-21swapper/119:07:361
1802724326,9sleep20-21swapper/219:05:212
63322380,1sleep30-21swapper/322:10:363
228602260,0sleep10-21swapper/121:23:261
1909799233,2cyclictest0-21swapper/321:16:343
1909799233,2cyclictest0-21swapper/320:31:533
1909699233,3cyclictest0-21swapper/200:33:402
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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