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2021-10-24 - 02:08

ARMv7 Processor rev 3 (v7l), Linux 5.10.52-rt47-v7l (Profile)

Latency plot of system in rack #4, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot1.osadl.org (updated Sun Oct 24, 2021 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1765021210,2sleep10-21swapper/123:07:401
1765021210,2sleep10-21swapper/123:07:401
796921200,2sleep1201rcuc/121:02:401
2675321150,4sleep30-21swapper/321:58:293
2675321150,4sleep30-21swapper/321:58:293
2675321150,4sleep30-21swapper/321:58:293
41552970,3sleep10-21swapper/122:27:491
41552970,3sleep10-21swapper/122:27:491
199612860,3sleep10-21swapper/123:17:161
199612860,3sleep10-21swapper/123:17:161
31922710,3chrt0-21swapper/300:02:483
31922710,3chrt0-21swapper/300:02:483
184642630,2sleep12434-21cyclictest19:57:421
184642630,2sleep12434-21cyclictest19:57:421
222032540,2sleep10-21swapper/123:22:391
281372520,3chrt0-21swapper/320:27:383
281372520,3chrt0-21swapper/320:27:383
312792500,2sleep331443-21sed23:47:423
246132500,3chrt0-21swapper/121:52:481
246132500,3chrt0-21swapper/121:52:481
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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