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2021-01-24 - 13:03

AMD Eng Sample: ZM277192H4468_36/27/15/06_130C, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #4, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack4slot1.osadl.org (updated Wed Jul 22, 2020 00:43:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
170002258118,93sleep20-21swapper/218:21:012
166982226118,97sleep30-21swapper/318:17:213
166532153118,26sleep00-21swapper/018:16:460
167992151119,23sleep10-21swapper/118:18:231
1148321110,2sleep30-21swapper/321:32:493
2252421070,2sleep01726099cyclictest18:31:250
312292920,2sleep20-21swapper/218:51:232
286812890,2sleep10-21swapper/123:34:221
296022880,2sleep10-21swapper/121:51:441
17260998073,5cyclictest942-21snmpd21:18:220
29512790,1sleep10-21swapper/123:41:231
17279997975,2cyclictest0-21swapper/319:43:013
1727099790,76cyclictest23996-21cat21:46:282
17279997874,2cyclictest18487-21ssh20:31:353
17279997874,2cyclictest18487-21ssh20:31:353
17279997874,2cyclictest0-21swapper/323:48:593
17260997872,1cyclictest942-21snmpd19:33:040
17260997865,7cyclictest942-21snmpd18:53:180
17260997865,7cyclictest942-21snmpd18:53:180
17279997774,2cyclictest0-21swapper/322:31:423
17260997771,1cyclictest942-21snmpd19:52:020
17260997764,7cyclictest942-21snmpd20:07:200
226402760,0sleep322643-21latency20:36:293
17279997673,2cyclictest0-21swapper/323:31:493
17265997674,1cyclictest0-21swapper/122:20:171
17265997674,1cyclictest0-21swapper/121:33:251
17265997674,1cyclictest0-21swapper/121:08:091
17260997665,5cyclictest942-21snmpd19:43:250
17279997572,1cyclictest0-21swapper/322:24:263
17279997571,2cyclictest0-21swapper/323:23:013
17279997571,2cyclictest0-21swapper/318:27:063
17270997573,1cyclictest0-21swapper/221:14:462
17279997472,1cyclictest0-21swapper/322:11:053
17279997471,1cyclictest0-21swapper/321:36:403
17279997471,1cyclictest0-21swapper/319:47:253
17270997472,1cyclictest0-21swapper/220:11:082
17265997472,1cyclictest0-21swapper/120:56:121
17279997370,1cyclictest0-21swapper/322:39:423
17279997370,1cyclictest0-21swapper/320:43:423
17279997370,1cyclictest0-21swapper/320:12:173
17270997370,2cyclictest0-21swapper/218:58:302
17265997371,1cyclictest0-21swapper/118:41:151
1726599730,71cyclictest942-21snmpd22:43:181
17265997270,1cyclictest0-21swapper/123:19:161
17265997270,1cyclictest0-21swapper/121:49:371
17265997270,1cyclictest0-21swapper/120:03:441
17260997264,6cyclictest942-21snmpd18:41:000
17279997165,3cyclictest26992-21if_p32p119:51:293
17265997169,1cyclictest0-21swapper/120:47:121
17265997169,1cyclictest0-21swapper/118:29:451
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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