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2022-07-01 - 00:32

ARM TI AM3354 @800 MHz, Linux 5.10.47-rt46 (Profile)

Latency plot of system in rack #4, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Command line: cyclictest -l50000000 -m -n -a0 -t1 -p99 -i400 -h400 -q
Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot2.osadl.org (updated Thu Jun 30, 2022 12:44:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
74502010,0irq/46-4a10000029494-21/usr/sbin/munin06:53:470
7350970,0irq/45-4a10000012629-1kworker/u3:312:24:470
31116999269,0cyclictest0-21swapper10:43:580
31116999256,0cyclictest0-21swapper08:34:380
31116999170,0cyclictest0-21swapper07:09:060
31116999158,0cyclictest0-21swapper06:59:240
31116999157,0cyclictest0-21swapper12:14:440
31116999057,0cyclictest0-21swapper11:54:310
31116999056,0cyclictest0-21swapper10:54:370
31116998963,0cyclictest0-21swapper08:13:440
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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