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2023-06-07 - 00:50

ARM TI AM3354 @800 MHz, Linux 5.10.47-rt46 (Profile)

Latency plot of system in rack #4, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Command line: cyclictest -l50000000 -m -n -a0 -t1 -p99 -i400 -h400 -q
Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot2.osadl.org (updated Tue Jun 06, 2023 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
74501600,0irq/46-4a1000005933-21/usr/sbin/munin06:58:450
6523999361,0cyclictest0-21swapper10:13:550
6523999357,0cyclictest0-21swapper07:39:290
7450920,0irq/46-4a1000009777-21ntp_states07:09:400
7450920,0irq/46-4a10000016852-1kworker/u3:007:31:470
6523999271,0cyclictest0-21swapper11:28:510
6523999270,0cyclictest0-21swapper08:23:470
6523999260,0cyclictest0-21swapper10:53:180
7450910,0irq/46-4a10000016745-21/usr/sbin/munin10:38:400
7450910,0irq/46-4a10000013031-21wc07:18:440
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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