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2024-07-27 - 04:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot2.osadl.org (updated Sat Jul 27, 2024 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
74502540,0irq/46-4a10000013258-1kworker/u3:119:06:500
187079912436,0cyclictest32746-21/usr/sbin/munin00:34:530
187079912434,0cyclictest27057-21aten_r4power_en22:44:250
187079912142,0cyclictest19297-21/usr/sbin/munin19:09:500
187079912132,0cyclictest3954-21mailstats20:00:090
187079912132,0cyclictest20689-21irqstats20:49:520
187079912130,0cyclictest24354-21/usr/sbin/munin22:35:090
187079912050,0cyclictest7350irq/45-4a10000000:04:470
187079912046,0cyclictest12-21ksoftirqd/023:24:420
187079912040,0cyclictest15289-21df_abs20:34:350
187079911940,0cyclictest0-21swapper00:25:060
187079911934,0cyclictest2454-21runrttasks19:55:260
187079911933,0cyclictest31857-21seq22:58:160
187079911933,0cyclictest30098-21runrttasks19:42:520
187079911933,0cyclictest27224-21chrt19:34:420
187079911932,0cyclictest31312-21sensors_temp21:20:090
187079911930,0cyclictest8308-21cpu20:14:290
187079911929,0cyclictest5605-21rt-features23:15:090
187079911929,0cyclictest24726-21chrt00:10:360
187079911929,0cyclictest17361-21meminfo20:39:590
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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