You are here: Home / Projects / QA Farm Realtime / Latency plots / 
2022-01-22 - 15:24

ARMv7 Processor rev 2 (v7l), Linux 5.10.47-rt46 (Profile)

Latency plot of system in rack #4, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Command line: cyclictest -l50000000 -m -n -a0 -t1 -p99 -i400 -h400 -q
Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack4slot2.osadl.org (updated Sat Jan 22, 2022 12:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
74502010,0irq/46-4a1000002935-21runrttasks07:03:580
31049913351,0cyclictest0-21swapper08:25:430
31049911058,0cyclictest0-21swapper10:15:570
3104999655,0cyclictest0-21swapper07:05:570
3104999460,0cyclictest0-21swapper09:01:040
3104999362,0cyclictest0-21swapper08:31:050
3104999258,0cyclictest0-21swapper08:01:080
3104999159,0cyclictest0-21swapper08:46:070
3104999157,0cyclictest0-21swapper11:25:530
3104999069,0cyclictest0-21swapper08:35:200
3104999069,0cyclictest0-21swapper07:41:010
3104999059,0cyclictest0-21swapper07:50:230
3104999058,0cyclictest0-21swapper12:10:410
3104999058,0cyclictest0-21swapper07:45:260
3104999058,0cyclictest0-21swapper07:10:480
3104999057,0cyclictest0-21swapper07:30:530
3104999056,0cyclictest0-21swapper09:10:550
3104998966,0cyclictest0-21swapper12:25:570
3104998956,0cyclictest0-21swapper11:16:010
3104998956,0cyclictest0-21swapper10:05:370
3104998955,0cyclictest0-21swapper10:35:580
3104998955,0cyclictest0-21swapper08:56:030
3104998868,0cyclictest0-21swapper11:36:100
3104998867,0cyclictest0-21swapper08:21:150
3104998856,0cyclictest0-21swapper09:55:580
3104998856,0cyclictest0-21swapper08:15:580
3104998855,0cyclictest0-21swapper11:10:540
7350870,0irq/45-4a1000002351-21chrt10:10:110
3104998657,0cyclictest0-21swapper08:10:420
3104998655,0cyclictest0-21swapper07:26:060
3104998654,0cyclictest0-21swapper12:05:200
3104998653,0cyclictest0-21swapper11:40:400
3104998653,0cyclictest0-21swapper07:21:060
3104998652,0cyclictest0-21swapper10:00:170
3104998652,0cyclictest0-21swapper09:20:460
3104998552,0cyclictest0-21swapper09:41:000
3104998551,0cyclictest0-21swapper10:20:350
7350840,0irq/45-4a10000015618-1kworker/u3:010:50:580
3104998451,0cyclictest0-21swapper11:20:270
3104998450,0cyclictest0-21swapper12:30:550
3104998350,0cyclictest0-21swapper09:45:480
3104998350,0cyclictest0-21swapper07:36:010
3104998349,0cyclictest0-21swapper11:06:030
3104998349,0cyclictest0-21swapper10:30:380
3104998348,0cyclictest0-21swapper12:01:000
7450820,0irq/46-4a1000007889-21perl08:51:010
7450820,0irq/46-4a1000007003-21kworker/u2:1010:40:420
7450820,0irq/46-4a1000004706-21chrt11:51:180
3104998261,0cyclictest0-21swapper10:45:330
3104998260,0cyclictest0-21swapper09:50:370
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional