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2024-07-27 - 07:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Sat Jul 27, 2024 00:49:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
228292620chrt46250irq/120-QMan09:24:361
228292620chrt46250irq/120-QMan09:24:361
228292620chrt46250irq/120-QMan09:24:361
71610rcu_preempt0-21swapper/021:35:090
71610rcu_preempt0-21swapper/021:35:090
46050530irq/122-QManpo20876-2109:24:360
46050470irq/122-QManpo0-210
2785299472cyclictest12887-21snmpd21:49:213
2785299472cyclictest12887-21snmpd21:49:213
2785199472cyclictest21537-21runrttasks00:06:402
2785199472cyclictest21537-21runrttasks00:06:402
71460rcu_preempt0-21swapper/000:35:570
71460rcu_preempt0-21swapper/000:35:570
71460rcu_preempt0-21swapper/000:35:570
2785199464cyclictest0-21swapper/220:24:012
2785199464cyclictest0-21swapper/220:24:012
2785199463cyclictest12887-21snmpd00:18:222
2785199463cyclictest12887-21snmpd00:18:222
2785199462cyclictest13528-1kworker/2:2H20:39:082
2785199462cyclictest13528-1kworker/2:2H20:39:082
2785199462cyclictest13528-1kworker/2:2H20:39:082
27852994519cyclictest22715-21meminfo21:08:593
27852994519cyclictest22715-21meminfo21:08:593
27852994519cyclictest22715-21meminfo21:08:593
71440rcu_preempt0-21swapper/021:08:470
71440rcu_preempt0-21swapper/021:08:470
71440rcu_preempt0-21swapper/021:08:470
2785299443cyclictest0-21swapper/322:38:543
2785299443cyclictest0-21swapper/322:38:543
2785299443cyclictest0-21swapper/322:38:543
27852994422cyclictest0-21swapper/322:18:453
27852994422cyclictest0-21swapper/322:18:453
2785199444cyclictest0-21swapper/223:28:382
2785199444cyclictest0-21swapper/223:28:382
2785199444cyclictest0-21swapper/222:13:472
2785199444cyclictest0-21swapper/222:13:472
2785199444cyclictest0-21swapper/222:13:472
2785199441cyclictest9781-21ntp_states22:49:032
2785199441cyclictest9781-21ntp_states22:49:032
71430rcu_preempt0-21swapper/120:55:041
71430rcu_preempt0-21swapper/120:55:041
71430rcu_preempt0-21swapper/120:55:041
46450430irq/118-QManpo20886-2109:24:362
27852994319cyclictest0-21swapper/321:53:523
27852994319cyclictest0-21swapper/321:53:523
27852994319cyclictest0-21swapper/321:53:523
27852994317cyclictest0-21swapper/323:21:223
27852994317cyclictest0-21swapper/323:21:223
27852994313cyclictest16745-21/usr/sbin/munin23:58:553
27852994313cyclictest16745-21/usr/sbin/munin23:58:553
27852994313cyclictest12449-21ssh00:48:483
27852994313cyclictest12449-21ssh00:48:483
27852994313cyclictest12449-21ssh00:48:483
2785199434cyclictest0-21swapper/223:34:022
2785199434cyclictest0-21swapper/223:34:022
2785199434cyclictest0-21swapper/222:40:072
2785199434cyclictest0-21swapper/222:40:072
2785199434cyclictest0-21swapper/222:40:072
2785199434cyclictest0-21swapper/220:44:062
2785199434cyclictest0-21swapper/220:44:062
2785199434cyclictest0-21swapper/219:49:062
2785199434cyclictest0-21swapper/219:49:062
2785199433cyclictest0-21swapper/222:09:102
2785199433cyclictest0-21swapper/222:09:102
2785199433cyclictest0-21swapper/222:01:042
2785199433cyclictest0-21swapper/222:01:042
2785199433cyclictest0-21swapper/222:01:042
2785199432cyclictest30808-1kworker/2:0H22:38:382
2785199432cyclictest30808-1kworker/2:0H22:38:382
2785199432cyclictest24261-21sort23:14:092
2785199432cyclictest24261-21sort23:14:092
2785199432cyclictest24261-21sort23:14:092
2785199432cyclictest22343-21aten_r4power_cu21:08:502
2785199432cyclictest22343-21aten_r4power_cu21:08:502
2785199432cyclictest22343-21aten_r4power_cu21:08:502
2785199432cyclictest12809-21ssh22:54:102
2785199432cyclictest12809-21ssh22:54:102
2785199431cyclictest5496-21latency_hist20:08:402
2785199431cyclictest5496-21latency_hist20:08:402
2785199431cyclictest19536-21/usr/sbin/munin20:59:052
2785199431cyclictest19536-21/usr/sbin/munin20:59:052
71420rcu_preempt0-21swapper/121:47:031
71420rcu_preempt0-21swapper/121:47:031
71420rcu_preempt0-21swapper/121:47:031
71420rcu_preempt0-21swapper/000:18:260
71420rcu_preempt0-21swapper/000:18:260
2785299424cyclictest0-21swapper/300:18:253
2785299424cyclictest0-21swapper/300:18:253
2785299423cyclictest0-21swapper/322:53:543
2785299423cyclictest0-21swapper/322:53:543
2785299422cyclictest6410-21aten_r4power_cu22:43:523
2785299422cyclictest6410-21aten_r4power_cu22:43:523
2785299422cyclictest2846-21/usr/sbin/munin19:59:073
2785299422cyclictest2846-21/usr/sbin/munin19:59:073
2785299422cyclictest2846-21/usr/sbin/munin19:59:073
2785299422cyclictest27748-21diskmemload23:43:593
2785299422cyclictest27748-21diskmemload23:43:593
2785299422cyclictest0-21swapper/323:23:573
2785299422cyclictest0-21swapper/323:23:573
2785199425cyclictest28073-1kworker/2:1H00:18:532
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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