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2023-05-28 - 05:44

PowerPC Freescale e5500 @1200 MHz, Linux 4.1.8-rt8+gbd51baffc04e (Profile)

Latency plot of system in rack #4, slot #4
Data to construct the above plot have been generated using the RT test utility cyclictest.
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Sun May 28, 2023 00:46:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71760rcu_preempt14365-21copy22:35:522
71760rcu_preempt14365-21copy22:35:522
941899514cyclictest0-21swapper/100:11:321
941899514cyclictest0-21swapper/100:11:321
71460rcu_preempt0-21swapper/322:23:343
71460rcu_preempt0-21swapper/322:23:343
71460rcu_preempt0-21swapper/223:55:572
71460rcu_preempt0-21swapper/223:55:572
71460rcu_preempt0-21swapper/223:55:572
71450rcu_preempt0-21swapper/320:51:023
71450rcu_preempt0-21swapper/320:51:023
941899444cyclictest0-21swapper/122:42:471
941899444cyclictest0-21swapper/122:42:471
71440rcu_preempt0-21swapper/221:48:032
71440rcu_preempt0-21swapper/221:48:032
941899434cyclictest25409-21irqstats22:56:171
941899434cyclictest25409-21irqstats22:56:171
941899434cyclictest0-21swapper/123:55:151
941899434cyclictest0-21swapper/123:55:151
941899434cyclictest0-21swapper/123:31:091
941899434cyclictest0-21swapper/123:31:091
941899434cyclictest0-21swapper/122:54:411
941899434cyclictest0-21swapper/122:54:411
941899434cyclictest0-21swapper/122:54:411
941899433cyclictest0-21swapper/122:27:381
941899433cyclictest0-21swapper/122:27:381
941899433cyclictest0-21swapper/122:27:381
941899433cyclictest0-21swapper/121:01:071
941899433cyclictest0-21swapper/121:01:071
941899433cyclictest0-21swapper/100:01:101
941899433cyclictest0-21swapper/100:01:101
941899433cyclictest0-21swapper/100:01:101
941899432cyclictest17018-21copy22:40:431
941899432cyclictest17018-21copy22:40:431
941899432cyclictest0-21swapper/120:06:001
941899432cyclictest0-21swapper/120:06:001
9418994321cyclictest0-21swapper/121:51:211
9418994321cyclictest0-21swapper/121:51:211
71430rcu_preempt23851-21copy23:55:480
71430rcu_preempt23851-21copy23:55:480
71430rcu_preempt23851-21copy23:55:480
941899424cyclictest0-21swapper/123:01:171
941899424cyclictest0-21swapper/123:01:171
941899424cyclictest0-21swapper/119:31:051
941899424cyclictest0-21swapper/100:16:201
941899424cyclictest0-21swapper/100:16:201
941899423cyclictest0-21swapper/122:16:071
941899423cyclictest0-21swapper/122:16:071
941899423cyclictest0-21swapper/121:31:051
941899423cyclictest0-21swapper/121:31:051
941899423cyclictest0-21swapper/121:31:051
941899423cyclictest0-21swapper/120:56:121
941899423cyclictest0-21swapper/120:56:121
941899423cyclictest0-21swapper/100:21:001
941899423cyclictest0-21swapper/100:21:001
941899422cyclictest18928-21df23:45:541
941899422cyclictest18928-21df23:45:541
941899422cyclictest18928-21df23:45:541
71420rcu_preempt0-21swapper/322:40:503
71420rcu_preempt0-21swapper/322:40:503
941899415cyclictest16270-21aten_r4power_vo23:40:591
941899415cyclictest16270-21aten_r4power_vo23:40:591
941899414cyclictest0-21swapper/122:48:561
941899414cyclictest0-21swapper/122:48:561
941899414cyclictest0-21swapper/122:48:561
941899414cyclictest0-21swapper/122:31:211
941899414cyclictest0-21swapper/122:31:211
941899414cyclictest0-21swapper/121:29:101
941899414cyclictest0-21swapper/121:29:101
941899414cyclictest0-21swapper/121:29:101
941899414cyclictest0-21swapper/119:45:371
941899414cyclictest0-21swapper/119:45:371
941899413cyclictest0-21swapper/123:26:081
941899413cyclictest0-21swapper/123:26:081
941899413cyclictest0-21swapper/123:17:001
941899413cyclictest0-21swapper/123:17:001
941899413cyclictest0-21swapper/123:17:001
941899413cyclictest0-21swapper/123:06:051
941899413cyclictest0-21swapper/123:06:051
941899413cyclictest0-21swapper/121:06:171
941899413cyclictest0-21swapper/121:06:171
941899413cyclictest0-21swapper/121:06:171
941899413cyclictest0-21swapper/120:31:111
941899413cyclictest0-21swapper/120:31:111
941899413cyclictest0-21swapper/119:50:551
941899413cyclictest0-21swapper/119:50:551
941899412cyclictest0-21swapper/122:21:071
941899412cyclictest0-21swapper/122:21:071
941899412cyclictest0-21swapper/121:36:181
941899412cyclictest0-21swapper/121:36:181
71410rcu_preempt0-21swapper/121:46:141
71410rcu_preempt0-21swapper/121:46:141
941899403cyclictest14946-21df_inode00:40:581
941899403cyclictest14946-21df_inode00:40:581
941899403cyclictest0-21swapper/123:56:121
941899403cyclictest0-21swapper/123:56:121
941899403cyclictest0-21swapper/123:56:121
941899403cyclictest0-21swapper/123:36:091
941899403cyclictest0-21swapper/123:36:091
941899403cyclictest0-21swapper/123:36:091
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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