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2025-07-13 - 12:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Sun Jul 13, 2025 00:53:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71610rcu_preempt0-21swapper/323:57:213
71610rcu_preempt0-21swapper/323:57:213
46050500irq/122-QManpo7161-2109:24:360
46050500irq/122-QManpo7161-2109:24:360
46050500irq/122-QManpo7161-2109:24:360
46050500irq/122-QManpo7161-2109:24:360
71450rcu_preempt0-21swapper/120:26:221
71450rcu_preempt0-21swapper/120:26:221
2380699444cyclictest0-21swapper/320:45:353
2380699444cyclictest0-21swapper/320:45:353
2380699444cyclictest0-21swapper/320:45:353
71430rcu_preempt0-21swapper/323:08:423
71430rcu_preempt0-21swapper/323:08:423
71420rcu_preempt0-21swapper/223:40:472
71420rcu_preempt0-21swapper/223:40:472
71420rcu_preempt0-21swapper/223:40:472
71420rcu_preempt0-21swapper/122:00:251
71420rcu_preempt0-21swapper/122:00:251
71420rcu_preempt0-21swapper/122:00:251
71420rcu_preempt0-21swapper/121:40:421
71420rcu_preempt0-21swapper/121:40:421
2380699424cyclictest0-21swapper/322:40:253
2380699424cyclictest0-21swapper/322:40:253
23806994218cyclictest0-21swapper/300:55:483
23806994218cyclictest0-21swapper/300:55:483
71410rcu_preempt0-21swapper/123:23:091
71410rcu_preempt0-21swapper/123:23:091
46650410irq/116-QManpo7305-2109:24:363
46650410irq/116-QManpo7305-2109:24:363
46650410irq/116-QManpo7305-2109:24:363
2380699414cyclictest0-21swapper/320:05:403
2380699414cyclictest0-21swapper/320:05:403
71400rcu_preempt0-21swapper/023:34:550
71400rcu_preempt0-21swapper/023:34:550
71400rcu_preempt0-21swapper/022:14:430
71400rcu_preempt0-21swapper/022:14:430
2380699403cyclictest0-21swapper/323:35:333
2380699403cyclictest0-21swapper/323:35:333
2380699403cyclictest0-21swapper/323:35:333
71390rcu_preempt4906-1kworker/2:0H00:06:102
71390rcu_preempt4906-1kworker/2:0H00:06:102
71390rcu_preempt0-21swapper/301:01:293
71390rcu_preempt0-21swapper/301:01:293
71390rcu_preempt0-21swapper/301:01:293
71390rcu_preempt0-21swapper/223:48:172
71390rcu_preempt0-21swapper/223:48:172
71390rcu_preempt0-21swapper/123:30:511
71390rcu_preempt0-21swapper/123:30:511
71390rcu_preempt0-21swapper/020:05:430
71390rcu_preempt0-21swapper/020:05:430
71390rcu_preempt0-21swapper/000:30:140
71390rcu_preempt0-21swapper/000:30:140
71390rcu_preempt0-21swapper/000:30:140
46050390irq/122-QManpo28387-2109:24:360
46050390irq/122-QManpo28387-2109:24:360
46050390irq/122-QManpo0-210
46050390irq/122-QManpo0-210
71380rcu_preempt23665-1kworker/0:1H20:05:150
71380rcu_preempt23665-1kworker/0:1H20:05:150
71380rcu_preempt20428-21sh22:30:263
71380rcu_preempt20428-21sh22:30:263
71380rcu_preempt17913-21ssh00:25:413
71380rcu_preempt17913-21ssh00:25:413
71380rcu_preempt17913-21ssh00:25:413
71380rcu_preempt0-21swapper/322:25:153
71380rcu_preempt0-21swapper/322:25:153
71380rcu_preempt0-21swapper/321:35:313
71380rcu_preempt0-21swapper/321:35:313
71380rcu_preempt0-21swapper/223:00:512
71380rcu_preempt0-21swapper/223:00:512
71380rcu_preempt0-21swapper/221:45:142
71380rcu_preempt0-21swapper/221:45:142
46250380irq/120-QManpo0-2109:24:361
46050380irq/122-QManpo9035-2109:24:360
46050380irq/122-QManpo9035-2109:24:360
46050380irq/122-QManpo8626-2109:24:360
46050380irq/122-QManpo8626-2109:24:360
46050380irq/122-QManpo8626-2109:24:360
46050380irq/122-QManpo31037-2109:24:360
46050380irq/122-QManpo31037-2109:24:360
99650370irq/38-i2c-mpc0-21swapper/000:03:260
99650370irq/38-i2c-mpc0-21swapper/000:03:260
99650370irq/38-i2c-mpc0-21swapper/000:03:260
71370rcu_preempt29781-21sh00:50:172
71370rcu_preempt22861-21copy22:35:262
71370rcu_preempt22861-21copy22:35:262
71370rcu_preempt22861-21copy22:35:262
71370rcu_preempt13957-21sh23:19:152
71370rcu_preempt13957-21sh23:19:152
71370rcu_preempt0-21swapper/323:00:353
71370rcu_preempt0-21swapper/323:00:353
71370rcu_preempt0-21swapper/322:27:563
71370rcu_preempt0-21swapper/322:27:563
71370rcu_preempt0-21swapper/222:48:442
71370rcu_preempt0-21swapper/222:48:442
71370rcu_preempt0-21swapper/221:54:162
71370rcu_preempt0-21swapper/221:54:162
71370rcu_preempt0-21swapper/221:54:162
71370rcu_preempt0-21swapper/121:28:431
71370rcu_preempt0-21swapper/121:28:431
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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