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2026-01-20 - 06:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack4slot4.osadl.org (updated Tue Jan 20, 2026 00:43:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
709721210chrt46450irq/118-QMan10:48:552
709721210chrt46450irq/118-QMan10:48:552
709721210chrt46450irq/118-QMan10:48:552
71710rcu_preempt0-21swapper/000:35:400
71710rcu_preempt0-21swapper/000:35:400
71580rcu_preempt6911-21apt-get21:21:090
71580rcu_preempt6911-21apt-get21:21:090
71580rcu_preempt6911-21apt-get21:21:090
3258499573cyclictest0-21swapper/023:29:120
3258499573cyclictest0-21swapper/023:29:120
3258499561cyclictest0-21swapper/000:12:310
3258499561cyclictest0-21swapper/000:12:310
32584995615cyclictest0-21swapper/022:01:240
32584995615cyclictest0-21swapper/022:01:240
71540rcu_preempt0-21swapper/021:59:440
71540rcu_preempt0-21swapper/021:59:440
71540rcu_preempt0-21swapper/021:59:440
3258499544cyclictest0-21swapper/000:20:210
3258499544cyclictest0-21swapper/000:20:210
3258499541cyclictest3089-21apt-get19:20:550
3258499541cyclictest3089-21apt-get19:20:550
3258499541cyclictest14201-21apt-get20:00:550
3258499541cyclictest14201-21apt-get20:00:550
3258499541cyclictest14105-21sh00:21:440
3258499541cyclictest14105-21sh00:21:440
3258499533cyclictest0-21swapper/020:41:060
3258499533cyclictest0-21swapper/020:41:060
32584995316cyclictest8637-21apt-get19:40:570
32584995316cyclictest8637-21apt-get19:40:570
3258499524cyclictest0-21swapper/020:26:030
3258499524cyclictest0-21swapper/020:26:030
3258499524cyclictest0-21swapper/020:26:030
3258499522cyclictest0-21swapper/022:30:450
3258499522cyclictest0-21swapper/022:30:450
3258499514cyclictest0-21swapper/023:46:080
3258499514cyclictest0-21swapper/023:46:080
3258499514cyclictest0-21swapper/021:20:500
3258499514cyclictest0-21swapper/021:20:500
3258499513cyclictest0-21swapper/021:28:480
3258499513cyclictest0-21swapper/021:28:480
3258499513cyclictest0-21swapper/021:28:480
3258499513cyclictest0-21swapper/020:35:460
3258499513cyclictest0-21swapper/020:35:460
3258499512cyclictest30265-1kworker/0:1H23:01:010
3258499512cyclictest30265-1kworker/0:1H23:01:010
3258499512cyclictest24187-21irqstats20:36:040
3258499512cyclictest24187-21irqstats20:36:040
3258499512cyclictest22305-21users21:46:170
3258499512cyclictest22305-21users21:46:170
3258499512cyclictest20563-21aten_r4power_po22:40:580
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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