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2024-04-16 - 16:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot6.osadl.org (updated Tue Apr 16, 2024 12:44:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32466521040,95pltrace0-21swapper/307:05:273
3246652950,80pltrace0-21swapper/207:05:172
285752860,83pltrace0-21swapper/607:10:026
279528042,10sleep40-21swapper/407:09:034
287027944,10sleep70-21swapper/707:09:477
258627460,10sleep10-21swapper/107:06:031
259026449,11sleep50-21swapper/507:06:075
273325945,10sleep00-21swapper/007:08:100
2041452280,0pltrace0-21swapper/712:29:557
2937752250,1pltrace0-21swapper/710:50:237
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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