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2025-07-06 - 00:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot6.osadl.org (updated Sat Jul 05, 2025 12:44:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12619521040,96pltrace0-21swapper/507:06:265
12619521040,96pltrace0-21swapper/507:06:255
15406521020,94pltrace0-21swapper/107:09:261
15406521020,94pltrace0-21swapper/107:09:251
1261952990,89pltrace0-21swapper/207:05:232
1261952990,89pltrace0-21swapper/207:05:232
1261952930,84pltrace0-21swapper/607:05:196
1261952930,84pltrace0-21swapper/607:05:186
1548726147,10sleep70-21swapper/707:08:177
1548726147,10sleep70-21swapper/707:08:177
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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