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2024-03-03 - 20:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack4slot6.osadl.org (updated Sun Mar 03, 2024 12:53:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2221:41:503709
26,21:41:283708
27,21:41:283707
27,21:41:283706
23,21:41:283705
27,21:41:283704
393,21:41:283703
543,21:41:283702
021:41:283698
0,21:41:283697
0,21:41:283696
0,21:41:283695
0,21:41:283694
0,21:41:283693
0,21:41:283692
0,21:41:283691
0,21:41:283690
0,21:41:283689
0,21:41:283688
0,21:41:283687
0,21:41:283686
0,21:41:283685
0,21:41:283684
0,21:41:283683
0,21:41:283682
0,21:41:283681
0,21:41:283680
0,21:41:283679
0,21:41:283678
0,21:41:283677
0,21:41:283676
0,21:41:283675
0,21:41:283674
0,21:41:283673
0,21:41:283672
0,21:41:283671
0,21:41:283670
0,21:41:283669
0,21:41:283668
0,21:41:283667
0,21:41:283666
0,21:41:283665
0,21:41:283664
0,21:41:283663
0,21:41:283662
0,21:41:283661
0,21:41:283660
0,21:41:283659
0,21:41:283658
0,21:41:283657
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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