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2023-05-31 - 07:17

x86 Intel Core i7-2600K @3400 MHz, Linux 5.9.0-rc2-rt1 (Profile)

Latency plot of system in rack #4, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h200 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack4slot6.osadl.org (updated Wed May 31, 2023 00:44:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3007699544541,2cyclictest25-21ksoftirqd/219:10:012
3006899537535,1cyclictest19-21ksoftirqd/119:10:011
3007699114112,1cyclictest25-21ksoftirqd/219:10:002
2963052880,83pltrace0-21swapper/519:07:285
2953927861,12sleep30-21swapper/319:06:153
449852750,4pltrace3006299cyclictest22:22:170
2969127448,12sleep60-21swapper/619:08:046
2982027155,12sleep00-21swapper/019:09:500
1075752700,1pltrace10762-21pltrace-run20:27:174
173692660,0sleep10-21swapper/122:35:301
13482650,1sleep70-21swapper/700:36:357
305032630,0sleep70-21swapper/722:50:207
2739226347,12sleep70-21swapper/719:05:087
217162630,0sleep60-21swapper/623:15:186
217162630,0sleep60-21swapper/623:15:186
1402352630,0pltrace0-21swapper/322:32:163
88192600,1sleep50-21swapper/522:26:225
2738926043,12sleep40-21swapper/419:05:044
3006299200,19cyclictest0-21swapper/023:15:320
3006299200,19cyclictest0-21swapper/023:15:310
3010799191,16cyclictest0-21swapper/720:06:527
287352190,0sleep30-21swapper/320:00:313
1220552190,4pltrace0-21swapper/519:33:415
915652180,6pltrace0-21swapper/521:57:125
2908552180,10pltrace30023-21cstates20:05:185
939252170,0pltrace9396-21tail19:27:164
903252170,6pltrace0-21swapper/521:19:245
3045952170,3pltrace0-21swapper/521:06:055
30107991711,4cyclictest0-21swapper/721:20:157
3008499171,4cyclictest0-21swapper/319:42:153
3006899171,4cyclictest0-21swapper/122:09:171
2951652170,5pltrace0-21swapper/500:37:055
2286352170,4pltrace0-21swapper/522:09:475
2068252170,4pltrace0-21swapper/500:26:565
1842352170,4pltrace0-21swapper/521:31:555
1637852170,3pltrace0-21swapper/520:39:545
1371352170,1pltrace0-21swapper/522:01:215
3236052160,9pltrace0-21swapper/121:44:071
30107991611,3cyclictest0-21swapper/723:49:537
30107991610,3cyclictest0-21swapper/720:57:367
3010799161,14cyclictest0-21swapper/722:31:527
30101991611,3cyclictest0-21swapper/623:54:196
3010199161,3cyclictest0-21swapper/623:44:116
3010199160,9cyclictest0-21swapper/619:26:546
3010199160,4cyclictest0-21swapper/620:38:126
30094991611,3cyclictest0-21swapper/520:49:025
30094991611,3cyclictest0-21swapper/520:20:015
30094991611,2cyclictest0-21swapper/522:38:215
30094991610,5cyclictest0-21swapper/523:52:235
3008999161,14cyclictest0-21swapper/400:17:094
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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