You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2024-04-26 - 18:01

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #4, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot7s.osadl.org (updated Fri Apr 26, 2024 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,6135
"cycles":100000000,6134
"load":"idle",6133
"condition":{6132
"clock":"1833"6130
"family":"x86",6129
"vendor":"Intel",6128
"processor":{6126
"dataset":"2024-01-08T15:39:05+01:00"6124
"origin":"2024-01-08T12:43:23+01:00",6123
"timestamps":{6122
"granularity":"microseconds"6120
4016:23:506118
51,16:24:016117
"maxima":[6116
016:23:106113
0,16:23:106112
0,16:23:106111
0,16:23:106110
0,16:23:106109
0,16:23:106108
0,16:23:106107
0,16:23:106106
0,16:23:106105
0,16:23:106104
0,16:23:106103
0,16:23:106102
0,16:23:106101
0,16:23:106100
0,16:23:106099
0,16:23:106098
0,16:23:106097
0,16:23:106096
0,16:23:106095
0,16:23:106094
0,16:23:106093
0,16:23:106092
0,16:23:106091
0,16:23:106090
0,16:23:106089
0,16:23:106088
0,16:23:106087
0,16:23:106086
0,16:23:106085
0,16:23:106084
0,16:23:106083
0,16:23:106082
0,16:23:106081
0,16:23:106080
0,16:23:106079
0,16:23:106078
0,16:23:106077
0,16:23:106076
0,16:23:106075
0,16:23:106074
0,16:23:106073
0,16:23:106072
0,16:23:106071
0,16:23:106070
0,16:23:106069
0,16:23:106068
0,16:23:106067
0,16:23:106066
0,16:23:106065
0,16:23:106064
0,16:23:106063
0,16:23:106062
0,16:23:106061
0,16:23:106060
0,16:23:106059
0,16:23:106058
0,16:23:106057
0,16:23:106056
0,16:23:106055
0,16:23:106054
0,16:23:106053
0,16:23:106052
0,16:23:106051
0,16:23:106050
0,16:23:106049
0,16:23:106048
0,16:23:106047
0,16:23:106046
0,16:23:106045
0,16:23:106044
0,16:23:106043
0,16:23:106042
0,16:23:106041
0,16:23:106040
0,16:23:106039
0,16:23:106038
0,16:23:106037
0,16:23:106036
0,16:23:106035
0,16:23:106034
0,16:23:106033
0,16:23:106032
0,16:23:106031
0,16:23:106030
0,16:23:106029
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional