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2024-09-13 - 00:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Thu Sep 12, 2024 12:44:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2819021420,4sleep22055199cyclictest12:32:022
1802121310,5sleep22055199cyclictest09:13:432
3168021290,1sleep10-21swapper/112:29:321
3176521110,4sleep12054799cyclictest10:00:031
20089210332,43sleep30-21swapper/307:07:293
2536821000,2sleep30-21swapper/311:10:423
178472960,2sleep20-21swapper/209:34:512
216422950,2sleep221641-21bash12:08:332
208072950,1sleep020786-21sshd09:44:030
2028029432,49sleep10-21swapper/107:09:481
2005929235,12sleep20-21swapper/207:07:082
285672910,1sleep028564-21sshd10:32:240
97562900,0sleep00-21swapper/009:25:030
8002900,2sleep20-21swapper/210:06:012
311522890,1sleep31848-21nfsd10:41:293
138502850,0sleep00-21swapper/011:12:440
19112830,1sleep00-21swapper/011:52:330
269562820,1sleep01846-21nfsd11:31:560
85542810,1sleep30-21swapper/311:15:163
294212810,2sleep30-21swapper/310:50:193
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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