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2021-09-28 - 09:54

Intel(R) Xeon(R) CPU E31220L @ 2.20GHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #5, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Tue Sep 28, 2021 00:44:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1299121240,3sleep10-21swapper/123:14:221
408121170,0sleep00-21swapper/022:47:200
2790821160,3sleep22891399cyclictest23:04:572
28529210532,44sleep10-21swapper/119:07:281
28731210432,44sleep30-21swapper/319:09:583
29442980,1sleep010-21rcuc/022:10:250
215632960,2sleep02891199cyclictest23:19:020
196072930,0sleep00-21swapper/020:00:140
39742900,2sleep10-21swapper/100:38:571
225882900,4sleep022582-21sshd21:46:570
19842890,1sleep22891399cyclictest22:43:242
97712870,1sleep00-21swapper/022:33:170
52192870,1sleep35207-21sshd22:03:233
174172860,2sleep20-21swapper/200:14:182
199422850,2sleep10-21swapper/100:18:171
15662830,2sleep20-21swapper/222:21:172
313852820,1sleep10-21swapper/121:47:581
236512820,1sleep30-21swapper/322:09:123
17732810,0sleep00-21swapper/022:35:570
12932800,3sleep30-21swapper/323:12:593
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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