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2025-06-24 - 18:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Tue Jun 24, 2025 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2408021780,4sleep31713999cyclictest12:33:323
1481121370,1sleep30-21swapper/309:48:073
726421340,1sleep07256-21rm09:47:200
1596721270,1sleep10-21swapper/110:51:051
2898321200,1sleep08-21rcu_preempt11:24:270
2898321200,1sleep08-21rcu_preempt11:24:260
1928921180,2sleep21846-21nfsd11:16:232
1928921180,2sleep21846-21nfsd11:16:222
1129421180,3sleep01713699cyclictest11:56:010
1838221060,3sleep31713999cyclictest12:39:373
2199821020,3sleep21713899cyclictest12:40:002
16684210233,40sleep10-21swapper/107:07:421
307532970,1sleep00-21swapper/010:27:240
44952940,1sleep10-21swapper/112:18:341
197762930,1sleep019774-21sshd12:36:210
200212920,1sleep00-21swapper/011:46:550
90322900,3sleep20-21swapper/210:50:222
242412900,2sleep20-21swapper/208:35:172
131372900,2sleep30-21swapper/309:13:523
1684828934,51sleep30-21swapper/307:09:443
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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