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2023-12-07 - 14:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Thu Dec 07, 2023 12:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2717521570,2sleep02055699cyclictest10:11:450
2766421340,2sleep21955-21snmpd09:51:522
838621170,1sleep02055699cyclictest11:59:410
838621170,1sleep02055699cyclictest11:59:410
847321090,2sleep30-21swapper/311:01:083
1492521020,1sleep02035-21lldpd-portmirro09:10:360
2157121000,2sleep221558-21sshd10:50:482
1784421000,4sleep32056999cyclictest09:58:413
1600121000,2sleep315999-21sshd11:53:033
1600121000,2sleep315999-21sshd11:53:023
83532990,2sleep18328-21sshd10:25:221
163002990,1sleep01955-21snmpd09:30:360
67472980,4sleep12056099cyclictest09:53:181
190522970,3sleep30-21swapper/309:23:023
56132960,4sleep22035-21lldpd-portmirro12:21:442
4342960,1sleep02035-21lldpd-portmirro11:35:450
204582950,1sleep10-21swapper/112:15:541
63362940,1sleep02021-21lldpd11:32:390
207322940,2sleep120721-21sshd09:43:041
275752930,1sleep30-21swapper/310:23:483
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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