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2023-06-03 - 20:31

x86 Intel Xeon-E31220L @2200 MHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #5, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Sat Jun 03, 2023 12:44:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2373121370,1sleep223707-21sshd11:18:262
1230421180,2sleep112293-21sshd11:20:341
3193521170,0sleep131936-21sshd10:32:131
1921021140,0sleep00-21swapper/010:24:140
73921080,3sleep30-21swapper/307:05:193
107972930,2sleep210795-21sshd10:50:132
62822890,5sleep00-21swapper/010:06:070
182242880,4sleep0219999cyclictest09:50:390
5282870,3sleep11876-21nfsd09:10:521
312682860,1sleep10-21swapper/111:52:561
198212850,1sleep019816-21sshd09:16:370
197828533,48sleep10-21swapper/107:09:581
27782830,1sleep02777-21seq11:39:530
189802830,2sleep318974-21sshd09:47:303
243272820,1sleep10-21swapper/111:48:511
81932810,1sleep30-21swapper/310:19:443
48662810,3sleep30-21swapper/309:36:003
170972810,1sleep10-21swapper/111:10:561
187912790,1sleep20-21swapper/210:34:142
237452780,2sleep323730-21sshd10:28:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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