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2025-01-16 - 06:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Wed Jan 15, 2025 12:44:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3091921420,0sleep130920-21sshd10:25:091
2636221340,2sleep30-21swapper/311:09:113
329521220,2sleep23281-21sshd12:29:382
171721220,4sleep11092599cyclictest09:32:561
35122980,2sleep11848-21nfsd11:58:511
98862960,2sleep29889-21tr09:50:072
29592910,1sleep30-21swapper/309:49:283
239442910,0sleep00-21swapper/011:57:410
73402880,2sleep11847-21nfsd11:28:411
210262870,0sleep00-21swapper/009:28:250
52812860,2sleep32405-21runrttasks09:59:313
277482860,3sleep10-21swapper/111:33:381
862328536,45sleep30-21swapper/307:05:093
214012850,2sleep221403-21id12:03:362
1050328433,47sleep10-21swapper/107:07:551
114622830,3sleep30-21swapper/311:32:033
7072820,2sleep20-21swapper/209:26:222
183422820,2sleep21847-21nfsd10:36:532
5702810,1sleep20-21swapper/211:37:072
42802810,2sleep30-21swapper/310:48:473
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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