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2019-07-17 - 02:58

Intel(R) Xeon(R) CPU E31220L @ 2.20GHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #5, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Wed Jul 17, 2019 00:44:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2714129435,39sleep10-21swapper/119:06:451
2718729230,58sleep30-21swapper/319:07:193
236262730,1sleep22117-21runrttasks22:39:142
2718626432,12sleep20-21swapper/219:07:182
2716025833,13sleep00-21swapper/019:06:590
155792540,1sleep015581-21unixbench_singl19:50:130
2764999233,7cyclictest145750irq/27-eth021:55:332
34152210,1sleep00-21swapper/019:25:090
2764999204,7cyclictest145750irq/27-eth022:56:482
2764999204,7cyclictest145750irq/27-eth022:33:482
2764999203,8cyclictest145750irq/27-eth023:03:202
2764999202,12cyclictest0-21swapper/221:11:012
2764999196,8cyclictest0-21swapper/222:40:272
2764999194,12cyclictest145750irq/27-eth023:07:012
2764999193,8cyclictest145750irq/27-eth000:08:012
2764999193,5cyclictest145750irq/27-eth023:13:052
2764999193,3cyclictest0-21swapper/222:00:102
2764999193,13cyclictest0-21swapper/221:45:032
2764999193,10cyclictest145750irq/27-eth020:54:012
27649991911,5cyclictest0-21swapper/223:17:452
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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