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2024-07-27 - 03:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Sat Jul 27, 2024 00:44:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2886521210,2sleep10-21swapper/122:35:241
453921190,3sleep2289999cyclictest22:03:462
195612950,1sleep00-21swapper/000:37:340
250629333,56sleep10-21swapper/119:08:211
246962910,2sleep224690-21sshd23:49:032
291652870,2sleep20-21swapper/222:05:542
257612860,2sleep30-21swapper/323:52:033
133292860,2sleep20-21swapper/221:26:242
99472850,2sleep20-21swapper/200:30:152
99472850,2sleep20-21swapper/200:30:152
64132850,2sleep30-21swapper/300:08:233
205482850,2sleep10-21swapper/100:09:461
244432840,3sleep0289099cyclictest00:07:000
4622830,1sleep0460-21seq23:29:010
151042830,1sleep20-21swapper/200:06:062
261228232,45sleep30-21swapper/319:09:383
114342820,2sleep111432-21sshd22:07:181
6422800,2sleep2643-21sshd23:05:192
289392800,2sleep30-21swapper/323:31:323
285092790,3sleep228505-21bash21:57:052
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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