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2025-02-19 - 00:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack5slot1.osadl.org (updated Tue Feb 18, 2025 12:44:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2427239940,0EcMasterDemoSyn2428229tAtEmLog_010:37:535
2371139920,0EcMasterDemoSyn2372129tAtEmLog_011:08:175
1891339920,0EcMasterDemoSyn1892329tAtEmLog_011:53:565
2195439900,0EcMasterDemoSyn2196429tAtEmLog_012:39:345
2105939900,0EcMasterDemoSyn2106929tAtEmLog_009:11:415
549139880,0EcMasterDemoSyn550129tAtEmLog_008:41:155
700939870,0EcMasterDemoSyn701929tAtEmLog_007:45:285
3009839860,0EcMasterDemoSyn3010829tAtEmLog_010:42:575
2299439850,0EcMasterDemoSyn2300429tAtEmLog_011:33:395
2299439850,0EcMasterDemoSyn2300429tAtEmLog_011:33:385
3040339840,0EcMasterDemoSyn3041329tAtEmLog_011:13:225
2965639840,0EcMasterDemoSyn2966629tAtEmLog_011:38:435
2800439840,0EcMasterDemoSyn2801429tAtEmLog_010:12:315
948539830,0EcMasterDemoSyn949529tAtEmLog_009:57:195
2914739830,0EcMasterDemoSyn2915729tAtEmLog_009:47:095
2682439830,0EcMasterDemoSyn2683429tAtEmLog_011:59:005
247139830,0EcMasterDemoSyn248229tAtEmLog_012:04:045
470339820,0EcMasterDemoSyn471329tAtEmLog_011:18:265
460839820,0EcMasterDemoSyn461829tAtEmLog_009:26:535
460839820,0EcMasterDemoSyn461829tAtEmLog_009:26:535
2918839820,0EcMasterDemoSyn2919829tAtEmLog_008:26:035
1848739820,0EcMasterDemoSyn1849829tAtEmLog_010:32:475
3234539810,0EcMasterDemoSyn3235529tAtEmLog_008:31:065
2088339810,0EcMasterDemoSyn2089329tAtEmLog_008:10:505
1776539800,0EcMasterDemoSyn1777529tAtEmLog_009:37:025
1654339800,0EcMasterDemoSyn1655329tAtEmLog_009:01:325
1095239790,0EcMasterDemoSyn1096229tAtEmLog_011:48:525
2124039780,0EcMasterDemoSyn2125029tAtEmLog_010:07:275
880939770,0EcMasterDemoSyn881929tAtEmLog_010:22:405
2364539770,0EcMasterDemoSyn2365529tAtEmLog_008:15:535
1622239770,0EcMasterDemoSyn1623229tAtEmLog_011:28:355
1530039770,0EcMasterDemoSyn1531029tAtEmLog_008:00:405
1376539760,0EcMasterDemoSyn1377529tAtEmLog_008:56:285
1239339760,0EcMasterDemoSyn1240329tAtEmLog_010:27:445
1100739760,0EcMasterDemoSyn1101729tAtEmLog_008:51:235
223539750,0EcMasterDemoSyn224529tAtEmLog_010:17:355
1910639750,0EcMasterDemoSyn1911529tAtEmLog_011:03:135
2364539730,4EcMasterDemoSyn1676499cyclictest08:15:530
45052650,1sleep1201rcuc/110:20:011
23752640,1sleep335-21ksoftirqd/309:24:353
123662600,0sleep60-21swapper/610:00:026
217862580,1sleep763-21ksoftirqd/710:35:217
1676599399,23cyclictest0-21swapper/108:51:231
1676499383,23cyclictest854-21rs:main0
1676499374,25cyclictest0-21swapper/009:15:120
16764993710,16cyclictest17398-21ps09:06:360
1676599357,16cyclictest8257-21ps08:46:181
16764993511,16cyclictest0-21swapper/010:53:040
1676499350,27cyclictest421-21systemd-journal10:37:510
1676499347,16cyclictest16549-21ps09:01:310
1676599336,16cyclictest421-21systemd-journal10:58:071
1676599328,16cyclictest0-21swapper/111:23:311
1676599328,16cyclictest0-21swapper/111:23:311
1676599325,16cyclictest421-21systemd-journal11:08:171
16764993210,15cyclictest0-21swapper/009:57:180
1676599319,16cyclictest0-21swapper/111:38:411
1676599318,16cyclictest0-21swapper/111:33:391
1676599318,16cyclictest0-21swapper/111:33:391
1676499319,15cyclictest0-21swapper/011:03:130
1676499318,15cyclictest0-21swapper/012:39:340
1676499318,15cyclictest0-21swapper/009:52:140
1676599308,15cyclictest0-21swapper/110:27:431
1676499307,15cyclictest0-21swapper/010:32:480
1676599297,15cyclictest0-21swapper/110:53:051
1676599297,15cyclictest0-21swapper/110:32:471
16765992910,16cyclictest0-21swapper/110:02:221
16764992825,2cyclictest240-21printk11:13:220
16766992725,2cyclictest240-21printk11:28:342
16765992725,2cyclictest240-21printk12:14:121
1676499270,16cyclictest854-21rs:main0
700939260,4EcMasterDemoSyn1676899cyclictest07:45:284
16766992625,1cyclictest240-21printk10:32:472
16766992625,1cyclictest240-21printk09:42:042
16766992625,1cyclictest240-21printk09:26:512
16766992625,1cyclictest240-21printk09:26:512
1676599262,16cyclictest854-21rs:main1
1676499263,16cyclictest0-21swapper/008:56:280
1676499263,16cyclictest0-21swapper/008:00:400
16764992623,2cyclictest240-21printk08:26:030
16767992524,1cyclictest240-21printk07:40:253
16767992524,1cyclictest240-21printk07:40:243
16766992524,1cyclictest240-21printk10:48:012
16766992524,1cyclictest240-21printk10:42:562
16766992524,1cyclictest240-21printk09:21:482
16766992522,2cyclictest240-21printk09:16:432
1676499253,13cyclictest0-21swapper/012:10:070
1676499252,16cyclictest0-21swapper/010:58:090
1676499251,16cyclictest0-21swapper/008:41:150
16768992423,1cyclictest240-21printk09:52:124
16768992423,1cyclictest240-21printk09:47:094
16768992423,1cyclictest240-21printk07:35:214
16768992423,1cyclictest240-21printk07:35:204
1676499248,8cyclictest0-21swapper/011:18:250
16764992423,1cyclictest240-21printk11:58:580
16764992423,1cyclictest240-21printk11:53:560
16764992423,1cyclictest240-21printk08:31:060
1676499241,16cyclictest0-21swapper/011:33:380
1676499241,16cyclictest0-21swapper/011:33:380
1676499240,16cyclictest0-21swapper/009:47:080
16768992322,1cyclictest240-21printk10:12:304
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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