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2024-07-27 - 03:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Sat Jul 27, 2024 00:44:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
262083984090,0EcMasterDemoSyn0-21swapper/523:53:135
75303984070,0EcMasterDemoSyn0-21swapper/521:23:445
135913984050,0EcMasterDemoSyn0-21swapper/522:54:045
234643984030,0EcMasterDemoSyn0-21swapper/522:59:315
168993984000,0EcMasterDemoSyn0-21swapper/521:28:495
300953983990,0EcMasterDemoSyn0-21swapper/520:17:395
227863983990,0EcMasterDemoSyn0-21swapper/522:24:215
82593983970,0EcMasterDemoSyn0-21swapper/523:08:355
164953983960,0EcMasterDemoSyn0-21swapper/521:10:415
19533983930,0EcMasterDemoSyn0-21swapper/522:12:435
75383983910,0EcMasterDemoSyn0-21swapper/520:28:335
275113983900,0EcMasterDemoSyn0-21swapper/519:06:305
170303983880,0EcMasterDemoSyn0-21swapper/520:38:435
326703983870,0EcMasterDemoSyn0-21swapper/519:12:185
113763983850,0EcMasterDemoSyn0-21swapper/519:58:465
210783983840,0EcMasterDemoSyn0-21swapper/520:09:185
153833983830,0EcMasterDemoSyn0-21swapper/522:37:235
263993983820,0EcMasterDemoSyn0-21swapper/522:43:335
19003983820,0EcMasterDemoSyn0-21swapper/519:48:365
17193983820,0EcMasterDemoSyn0-21swapper/500:32:025
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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