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2026-02-09 - 15:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Mon Feb 09, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20482391620,0EcMasterDemoSyn20487-21runintdemo5min12:10:123
2017439910,0EcMasterDemoSyn2018429tAtEmLog_011:34:435
1665639910,0EcMasterDemoSyn1666629tAtEmLog_009:27:565
160939910,0EcMasterDemoSyn161929tAtEmLog_007:26:155
1537039900,1EcMasterDemoSyn15376-21ps09:07:391
721739870,6EcMasterDemoSyn7225-21grep09:58:223
718139840,0EcMasterDemoSyn719129tAtEmLog_010:33:525
1360539830,0EcMasterDemoSyn1361529tAtEmLog_007:51:365
2141539820,0EcMasterDemoSyn2142529tAtEmLog_009:12:445
1537039820,0EcMasterDemoSyn1538029tAtEmLog_009:07:395
2897939810,0EcMasterDemoSyn2898929tAtEmLog_007:16:065
272539810,0EcMasterDemoSyn273529tAtEmLog_009:38:055
2488939570,0EcMasterDemoSyn2489929tAtEmLog_011:24:335
2110039370,1EcMasterDemoSyn21106-21ps09:48:120
961639220,1EcMasterDemoSyn9624-21runintdemo5min08:52:271
2986729210,0tAtEmLog_00-21swapper/511:09:205
144352200,0sleep40-21swapper/409:44:554
2465399190,7cyclictest17830-21sh12:08:451
126662190,0sleep00-21swapper/011:47:560
3020739180,0EcMasterDemoSyn0-21swapper/508:27:055
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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