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2025-01-23 - 22:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Thu Jan 23, 2025 12:44:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18796391360,3EcMasterDemoSyn889599cyclictest11:12:273
470139940,0EcMasterDemoSyn471129tAtEmLog_011:02:185
2930839910,0EcMasterDemoSyn2931829tAtEmLog_010:57:145
2585839890,0EcMasterDemoSyn2586829tAtEmLog_011:58:055
2160739880,0EcMasterDemoSyn2161729tAtEmLog_008:30:115
2448039870,0EcMasterDemoSyn2449129tAtEmLog_012:38:395
1060139860,0EcMasterDemoSyn1061129tAtEmLog_009:05:415
3188239840,0EcMasterDemoSyn3189229tAtEmLog_008:45:245
2703339840,0EcMasterDemoSyn2704329tAtEmLog_010:11:365
1451239840,0EcMasterDemoSyn1452229tAtEmLog_009:36:065
179339830,0EcMasterDemoSyn180329tAtEmLog_008:50:295
1649039830,0EcMasterDemoSyn1650029tAtEmLog_012:13:185
1608139830,0EcMasterDemoSyn1609129tAtEmLog_008:20:035
2858539820,0EcMasterDemoSyn2859529tAtEmLog_008:40:205
2551939820,0EcMasterDemoSyn2552929tAtEmLog_007:39:295
2133539820,0EcMasterDemoSyn2134529tAtEmLog_009:15:505
1980239820,0EcMasterDemoSyn1981229tAtEmLog_007:29:205
140639820,0EcMasterDemoSyn141629tAtEmLog_007:54:415
904739810,0EcMasterDemoSyn905729tAtEmLog_011:47:575
3252639810,0EcMasterDemoSyn3253629tAtEmLog_010:36:585
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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