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2022-01-26 - 12:19

Intel(R) Core(TM) i7 CPU X 980 @ 3.33GHz, Linux 5.4.17-rt9 (Profile)

Latency plot of system in rack #5, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Command line: cyclictest -l100000000 -m -n -a -t5 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack5slot1.osadl.org (updated Wed Jan 26, 2022 00:44:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
318942560,1sleep00-21swapper/019:35:000
57312550,1sleep442-21ksoftirqd/400:25:014
1872939340,1EcMasterDemoSyn0-21swapper/123:40:401
390939180,0EcMasterDemoSyn0-21swapper/520:53:225
2011739180,0EcMasterDemoSyn0-21swapper/521:28:525
2907839170,0EcMasterDemoSyn0-21swapper/519:27:115
2753939160,0EcMasterDemoSyn2807450irq/17-atemsys22:55:035
64802150,0sleep10-21swapper/121:00:001
256539150,0EcMasterDemoSyn0-21swapper/523:10:165
981639140,1EcMasterDemoSyn0-21swapper/500:31:245
855739140,0EcMasterDemoSyn0-21swapper/519:52:325
487839140,0EcMasterDemoSyn0-21swapper/523:15:215
394039140,0EcMasterDemoSyn0-21swapper/519:42:235
3033439140,0EcMasterDemoSyn0-21swapper/500:06:045
2802039140,0EcMasterDemoSyn0-21swapper/500:00:595
2013399140,13cyclictest0-21swapper/323:05:243
2013399140,13cyclictest0-21swapper/323:05:243
1319539140,0EcMasterDemoSyn0-21swapper/520:02:415
127039140,1EcMasterDemoSyn0-21swapper/519:37:205
1086639140,1EcMasterDemoSyn0-21swapper/519:57:365
887439130,0EcMasterDemoSyn0-21swapper/522:14:305
855039130,0EcMasterDemoSyn0-21swapper/521:03:315
784839130,0EcMasterDemoSyn0-21swapper/523:20:245
750739130,0EcMasterDemoSyn0-21swapper/500:26:205
624939130,0EcMasterDemoSyn0-21swapper/519:47:285
52239130,0EcMasterDemoSyn0-21swapper/500:11:075
519839130,0EcMasterDemoSyn0-21swapper/500:21:175
425639130,0EcMasterDemoSyn0-21swapper/522:04:215
3268639130,0EcMasterDemoSyn0-21swapper/523:05:115
3268639130,0EcMasterDemoSyn0-21swapper/523:05:115
3204839130,0EcMasterDemoSyn0-21swapper/521:54:135
3139039130,0EcMasterDemoSyn0-21swapper/519:32:155
3037939130,0EcMasterDemoSyn0-21swapper/523:00:085
2974739130,0EcMasterDemoSyn0-21swapper/521:49:085
2938939130,0EcMasterDemoSyn0-21swapper/520:38:105
286439130,0EcMasterDemoSyn0-21swapper/500:16:115
2743039130,0EcMasterDemoSyn0-21swapper/521:44:045
2707939130,0EcMasterDemoSyn0-21swapper/520:33:065
2677039130,0EcMasterDemoSyn0-21swapper/519:22:075
2677039130,0EcMasterDemoSyn0-21swapper/519:22:075
2567439130,0EcMasterDemoSyn0-21swapper/523:55:555
2510039130,0EcMasterDemoSyn0-21swapper/521:39:005
2509739130,0EcMasterDemoSyn0-21swapper/522:50:005
2444139130,0EcMasterDemoSyn0-21swapper/519:17:035
2335639130,0EcMasterDemoSyn0-21swapper/523:50:505
2277839130,0EcMasterDemoSyn0-21swapper/522:44:555
2245439130,0EcMasterDemoSyn0-21swapper/520:22:575
2243639130,0EcMasterDemoSyn0-21swapper/521:33:565
2211939130,0EcMasterDemoSyn0-21swapper/519:11:595
2211939130,0EcMasterDemoSyn0-21swapper/519:11:595
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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