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2024-06-19 - 10:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot2.osadl.org (updated Wed Jun 19, 2024 00:44:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
171142204189,10sleep10-21swapper/119:08:441
171502184168,12sleep00-21swapper/019:09:110
149962183167,12sleep30-21swapper/319:05:103
17001210487,13sleep20-21swapper/219:07:162
92792510,1sleep2291rcuc/221:00:172
124352470,0sleep00-21swapper/022:29:390
268222460,0sleep30-21swapper/322:20:183
55272440,0sleep00-21swapper/021:21:220
218012440,0sleep30-21swapper/321:14:043
178972440,0sleep30-21swapper/322:31:473
138602440,0sleep00-21swapper/022:45:410
10732440,0sleep30-21swapper/320:45:133
195202430,0sleep10-21swapper/122:00:221
145062100,0sleep10-21swapper/121:58:101
29150290,0sleep00-21swapper/000:15:000
17930290,0sleep10-21swapper/122:48:151
174539991,7cyclictest0-21swapper/320:40:113
174249991,4cyclictest23369-21munin-run21:15:010
174249970,7cyclictest0-21swapper/023:05:130
2588260,0sleep10-21swapper/123:12:521
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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