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2026-01-20 - 07:30
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot2.osadl.org (updated Tue Jan 20, 2026 00:44:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
323002194178,12sleep00-21swapper/019:07:530
324252185168,12sleep10-21swapper/119:09:321
322732185168,12sleep30-21swapper/319:07:333
321962143124,14sleep20-21swapper/219:06:362
275522450,0sleep20-21swapper/222:29:572
244602450,0sleep30-21swapper/300:05:143
114652440,0sleep10-21swapper/100:30:261
240862430,0sleep20-21swapper/221:39:482
102252420,0sleep20-21swapper/223:41:272
18157290,0sleep018158-21diskmemload23:29:560
9124270,0sleep30-21swapper/300:13:383
326169971,3cyclictest206-21systemd-journal21:20:010
326269964,1cyclictest31-21ksoftirqd/221:15:022
326269960,1cyclictest17942-21ssh23:13:172
326229961,3cyclictest0-21swapper/119:40:121
326169962,4cyclictest30759-21sendmail23:20:000
326169960,3cyclictest10779-21awk19:30:010
326319955,0cyclictest0-21swapper/322:26:093
326319951,3cyclictest728-21snmpd23:10:193
326319950,5cyclictest0-21swapper/322:38:053
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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