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2024-10-03 - 22:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot2.osadl.org (updated Thu Oct 03, 2024 12:44:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
298922192176,12sleep00-21swapper/007:08:150
297662178162,11sleep10-21swapper/107:06:351
299762175158,13sleep20-21swapper/207:09:222
299772174157,12sleep30-21swapper/307:09:223
184232480,0sleep10-21swapper/110:56:311
304882460,0sleep00-21swapper/010:46:290
215732450,0sleep10-21swapper/109:55:101
226562440,0sleep2291rcuc/212:35:122
24382430,0sleep10-21swapper/109:30:081
229212410,0sleep10-21swapper/109:24:151
156892410,0sleep10-21swapper/111:27:101
252652150,0sleep00-21swapper/010:28:240
27042100,0sleep22665-21ssh12:25:122
17755290,0sleep20-21swapper/211:28:272
302159960,1cyclictest2889-21ssh10:33:182
302069965,1cyclictest0-21swapper/012:00:250
302209955,0cyclictest326-21kworker/3:209:19:463
302209951,3cyclictest0-21swapper/309:50:113
302209951,2cyclictest0-21swapper/311:10:103
302209950,5cyclictest0-21swapper/311:48:383
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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