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2022-05-26 - 20:06

x86 Intel Core i5-6440EQ @2700 MHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #5, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot2.osadl.org (updated Fri May 20, 2022 00:44:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
53662201185,11sleep10-21swapper/119:09:521
51702193176,12sleep00-21swapper/019:07:220
53682179162,12sleep30-21swapper/319:09:543
50882172156,11sleep20-21swapper/219:06:202
83362500,0sleep30-21swapper/300:10:163
302842470,0sleep20-21swapper/219:55:202
243142130,0sleep10-21swapper/122:22:121
275362110,0sleep10-21swapper/121:45:131
63032100,0sleep20-21swapper/200:09:472
22392100,0sleep10-21swapper/121:30:121
104962100,0sleep00-21swapper/021:35:110
55639970,7cyclictest0-21swapper/323:15:113
55489965,1cyclictest0-21swapper/019:50:110
55489960,3cyclictest4495-21munin-run22:50:010
18637260,0sleep00-21swapper/022:58:140
6882250,0sleep30-21swapper/322:11:253
55639955,0cyclictest0-21swapper/323:00:123
55639951,2cyclictest0-21swapper/323:45:123
55639951,2cyclictest0-21swapper/319:55:113
55639950,5cyclictest0-21swapper/319:46:143
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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