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2020-12-04 - 08:56
[ 43.060] (II) VESA: driver for VESA chipsets: vesa

Intel(R) Xeon(R) CPU E3-1578L v5 @ 2.00GHz, Linux 4.19.1-rt3 (Profile)

Latency plot of system in rack #5, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack5slot3.osadl.org (updated Fri Dec 04, 2020 00:50:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22252994644,1cyclictest0-21swapper/319:45:033
22256994241,0cyclictest0-21swapper/520:55:035
22255993939,0cyclictest0-21swapper/420:00:084
22255993332,1cyclictest8335-21apt-get20:45:014
22223993131,0cyclictest0-21swapper/021:05:010
2225599300,0cyclictest0-21swapper/419:50:024
2225299300,28cyclictest0-21swapper/319:35:023
22223993030,0cyclictest0-21swapper/023:20:090
22257992927,1cyclictest0-21swapper/600:30:076
2225799290,1cyclictest0-21swapper/619:35:036
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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