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2022-05-25 - 21:38

x86 Intel Xeon i3-1578L v5 @2000 MHz, Linux 4.19.1-rt3 (Profile)

Latency plot of system in rack #5, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack5slot3.osadl.org (updated Fri May 20, 2022 00:49:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19207992929,0cyclictest0-21swapper/522:16:495
19188992625,1cyclictest0-21swapper/323:43:343
19207991918,0cyclictest71950irq/125-eth022:42:425
19188991916,2cyclictest1690-21sendmail-mta21:50:183
1920799185,11cyclictest0-21swapper/519:30:015
19207991818,0cyclictest71950irq/125-eth023:36:025
19199991810,0cyclictest0-21swapper/423:20:164
19170991816,1cyclictest13059-21ssh22:24:260
19170991811,3cyclictest0-21swapper/020:30:000
19216991715,2cyclictest13032-21nscd00:35:346
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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