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2023-02-06 - 23:37

x86 Intel Xeon i3-1578L v5 @2000 MHz, Linux 4.19.246-rt110 (Profile)

Latency plot of system in rack #5, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack5slot3.osadl.org (updated Mon Feb 06, 2023 12:50:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27720994646,0cyclictest0-21swapper/612:20:256
27726994444,0cyclictest0-21swapper/707:30:357
2768199440,2cyclictest14019-21cut08:40:200
27708993937,1cyclictest0-21swapper/408:40:214
2772099340,0cyclictest0-21swapper/607:35:146
27701993432,1cyclictest0-21swapper/307:10:123
27726993333,0cyclictest0-21swapper/708:45:197
27695993333,0cyclictest0-21swapper/207:35:152
27713993030,0cyclictest0-21swapper/509:00:165
27708992929,0cyclictest0-21swapper/408:00:194
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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