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2022-06-27 - 17:39

x86 Intel Xeon i3-1578L v5 @2000 MHz, Linux 4.19.246-rt110 (Profile)

Latency plot of system in rack #5, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot3.osadl.org (updated Mon Jun 27, 2022 12:49:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
938993433,1cyclictest0-21swapper/307:25:103
917992929,0cyclictest0-21swapper/007:50:160
962992827,0cyclictest0-21swapper/707:50:107
933992727,0cyclictest0-21swapper/208:05:162
950992524,1cyclictest0-21swapper/508:50:195
950992521,3cyclictest561ktimersoftd/507:35:225
962992424,0cyclictest0-21swapper/709:05:187
933992414,9cyclictest725-21ptp4l10:22:452
962992321,1cyclictest3314-21idleruntime-cro07:15:007
955992323,0cyclictest0-21swapper/607:35:106
950992321,1cyclictest18258-21sendmail-msp09:40:015
95099227,8cyclictest561ktimersoftd/507:55:115
938992221,0cyclictest0-21swapper/307:35:103
962992121,0cyclictest0-21swapper/707:35:027
962992120,1cyclictest17965-21apt-get07:40:127
938992115,5cyclictest0-21swapper/310:20:183
933992010,4cyclictest0-21swapper/208:50:232
933992010,0cyclictest0-21swapper/207:10:222
962991910,4cyclictest0-21swapper/708:50:227
955991910,3cyclictest0-21swapper/607:30:226
945991910,2cyclictest0-21swapper/408:50:234
938991910,3cyclictest0-21swapper/309:00:213
938991910,2cyclictest0-21swapper/308:10:113
938991910,0cyclictest0-21swapper/309:37:533
933991910,2cyclictest0-21swapper/207:50:102
933991910,0cyclictest0-21swapper/207:35:132
926991910,4cyclictest0-21swapper/107:45:231
917991910,9cyclictest0-21swapper/010:23:420
917991910,3cyclictest0-21swapper/007:25:180
962991810,1cyclictest0-21swapper/707:30:117
962991810,0cyclictest0-21swapper/709:35:527
96299180,0cyclictest0-21swapper/708:05:457
955991810,4cyclictest0-21swapper/609:36:336
955991810,3cyclictest0-21swapper/610:20:216
955991810,2cyclictest0-21swapper/609:00:216
955991810,2cyclictest0-21swapper/607:25:206
955991810,0cyclictest0-21swapper/609:50:156
955991810,0cyclictest0-21swapper/608:50:236
955991810,0cyclictest0-21swapper/607:10:226
95599180,17cyclictest0-21swapper/610:55:036
945991813,1cyclictest17600-21idleruntime-cro07:40:014
938991810,2cyclictest0-21swapper/308:05:213
933991810,4cyclictest0-21swapper/207:25:222
933991810,0cyclictest0-21swapper/207:45:232
926991810,7cyclictest0-21swapper/107:35:211
926991810,2cyclictest0-21swapper/107:25:211
917991810,3cyclictest0-21swapper/007:35:100
917991810,0cyclictest0-21swapper/007:45:230
962991712,3cyclictest3381-21munin-node11:25:437
962991710,4cyclictest0-21swapper/707:55:117
962991710,2cyclictest0-21swapper/710:22:577
955991710,2cyclictest0-21swapper/608:55:006
950991710,2cyclictest0-21swapper/510:20:235
950991710,0cyclictest0-21swapper/510:10:405
945991710,5cyclictest0-21swapper/410:23:114
945991710,4cyclictest0-21swapper/407:45:234
938991710,5cyclictest0-21swapper/309:10:043
938991710,2cyclictest0-21swapper/307:45:203
93399172,6cyclictest0-21swapper/207:30:112
93399170,8cyclictest0-21swapper/209:00:212
926991717,0cyclictest0-21swapper/109:45:151
926991710,4cyclictest0-21swapper/110:21:331
926991710,4cyclictest0-21swapper/109:35:211
926991710,2cyclictest0-21swapper/109:00:161
926991710,0cyclictest0-21swapper/107:10:211
917991710,7cyclictest0-21swapper/009:39:110
917991710,0cyclictest0-21swapper/008:10:110
962991615,1cyclictest4136-21ssh10:29:597
962991615,1cyclictest3694-21sh09:50:167
962991610,2cyclictest0-21swapper/707:20:197
955991610,6cyclictest0-21swapper/612:27:366
955991610,3cyclictest0-21swapper/607:50:186
955991610,2cyclictest0-21swapper/610:25:126
955991610,2cyclictest0-21swapper/608:05:196
950991610,6cyclictest0-21swapper/511:13:165
950991610,3cyclictest0-21swapper/509:00:215
945991615,1cyclictest32590-21ssh09:48:044
945991615,1cyclictest32005-21ssh11:44:404
945991615,1cyclictest15741-21ssh09:57:104
945991610,4cyclictest0-21swapper/407:10:214
945991610,3cyclictest0-21swapper/409:35:364
945991610,2cyclictest0-21swapper/408:10:014
945991610,0cyclictest0-21swapper/410:58:314
938991610,4cyclictest0-21swapper/307:35:013
938991610,2cyclictest0-21swapper/307:50:213
938991610,0cyclictest0-21swapper/312:31:103
938991610,0cyclictest0-21swapper/309:05:213
938991610,0cyclictest0-21swapper/307:20:103
933991614,0cyclictest618-21diskmemload09:32:292
933991610,3cyclictest0-21swapper/209:10:012
933991610,3cyclictest0-21swapper/208:55:102
933991610,2cyclictest0-21swapper/209:35:242
933991610,1cyclictest0-21swapper/210:25:082
926991610,3cyclictest0-21swapper/107:30:111
926991610,3cyclictest0-21swapper/107:20:201
926991610,2cyclictest0-21swapper/108:50:231
926991610,1cyclictest0-21swapper/110:25:081
926991610,0cyclictest0-21swapper/108:05:221
917991614,0cyclictest13948-21ls08:30:200
917991610,3cyclictest0-21swapper/007:20:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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