You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-05-20 - 02:45
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot3.osadl.org (updated Tue May 20, 2025 00:50:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1213428353,26sleep40-21swapper/419:07:224
1219828064,11sleep30-21swapper/319:08:163
1212827843,30sleep00-21swapper/019:07:180
1206927844,30sleep60-21swapper/619:06:266
1200827743,29sleep10-21swapper/119:05:331
268142760,0sleep60-21swapper/622:45:246
1210627642,29sleep50-21swapper/519:06:585
1204727438,30sleep20-21swapper/219:06:062
1205227339,30sleep70-21swapper/719:06:117
20612630,0sleep10-21swapper/121:46:591
6392460,0sleep50-21swapper/520:35:125
149372460,0sleep10-21swapper/123:43:081
21842450,1sleep51275499cyclictest23:05:165
1232224542,1sleep30-21swapper/319:10:003
235412430,0sleep70-21swapper/723:00:157
12751993333,0cyclictest0-21swapper/223:32:392
12755992910,18cyclictest0-21swapper/622:38:456
12755992610,14cyclictest121rcu_preempt23:44:326
12749992424,0cyclictest0-21swapper/022:02:190
12755992311,9cyclictest121rcu_preempt00:16:576
12751992310,4cyclictest0-21swapper/219:10:102
12755992210,9cyclictest121rcu_preempt22:29:026
12756992117,4cyclictest1642-21ntpd23:49:507
12756992117,4cyclictest1642-21ntpd23:49:507
12755992111,8cyclictest121rcu_preempt00:20:126
12755992111,6cyclictest121rcu_preempt22:42:526
12755992111,6cyclictest121rcu_preempt21:45:156
12755992110,9cyclictest121rcu_preempt23:59:166
12755992110,9cyclictest121rcu_preempt23:53:336
12755992110,9cyclictest0-21swapper/600:36:566
12755992110,8cyclictest121rcu_preempt21:22:326
12755992110,6cyclictest121rcu_preempt22:06:346
12753992120,1cyclictest69450irq/124-eth022:05:204
12755992013,5cyclictest121rcu_preempt21:34:356
12755992012,3cyclictest121rcu_preempt00:27:176
12755992010,8cyclictest121rcu_preempt23:33:346
12755992010,8cyclictest121rcu_preempt22:22:156
12755992010,8cyclictest121rcu_preempt19:15:116
12755992010,8cyclictest121rcu_preempt19:15:016
12755992010,7cyclictest121rcu_preempt23:50:006
12755992010,7cyclictest121rcu_preempt23:50:006
12755992010,7cyclictest121rcu_preempt20:30:126
12755991913,5cyclictest121rcu_preempt21:58:246
12755991911,6cyclictest121rcu_preempt21:35:326
12755991911,5cyclictest121rcu_preempt19:25:256
12755991911,3cyclictest121rcu_preempt00:09:286
12755991910,9cyclictest0-21swapper/621:25:446
12755991910,7cyclictest121rcu_preempt23:25:016
12755991910,7cyclictest121rcu_preempt23:10:196
12755991910,7cyclictest121rcu_preempt22:55:196
12755991910,7cyclictest121rcu_preempt22:50:126
12755991910,7cyclictest121rcu_preempt22:00:176
12755991910,7cyclictest121rcu_preempt21:00:156
12755991910,7cyclictest121rcu_preempt20:00:136
12755991910,7cyclictest121rcu_preempt00:10:436
12755991910,6cyclictest121rcu_preempt23:35:496
12755991910,6cyclictest121rcu_preempt23:25:136
12755991910,6cyclictest121rcu_preempt23:19:456
12755991910,6cyclictest121rcu_preempt23:06:476
12755991910,6cyclictest121rcu_preempt22:15:126
12755991910,6cyclictest121rcu_preempt22:10:266
12755991910,6cyclictest121rcu_preempt21:05:166
12755991910,6cyclictest121rcu_preempt20:20:126
12753991918,1cyclictest69450irq/124-eth023:47:564
12753991918,1cyclictest69450irq/124-eth023:47:564
12749991919,0cyclictest24640-21ssh00:03:510
1898121810,0sleep20-21swapper/223:13:552
12756991816,1cyclictest662-21ptp4l00:13:157
12756991813,1cyclictest1642-21ntpd00:34:417
12756991810,8cyclictest0-21swapper/700:39:577
12755991811,5cyclictest121rcu_preempt21:50:016
12755991811,5cyclictest121rcu_preempt20:45:126
12755991810,6cyclictest121rcu_preempt23:00:386
12755991810,6cyclictest121rcu_preempt22:30:226
12755991810,6cyclictest121rcu_preempt21:40:046
12755991810,6cyclictest121rcu_preempt21:15:166
12755991810,6cyclictest121rcu_preempt21:10:266
12755991810,6cyclictest121rcu_preempt20:55:166
12755991810,6cyclictest121rcu_preempt20:50:146
12755991810,6cyclictest121rcu_preempt20:40:126
12755991810,6cyclictest121rcu_preempt20:35:226
12755991810,6cyclictest121rcu_preempt20:25:156
12755991810,6cyclictest121rcu_preempt20:10:136
12755991810,6cyclictest121rcu_preempt19:55:166
12755991810,6cyclictest121rcu_preempt19:50:226
12755991810,6cyclictest121rcu_preempt19:40:146
12755991810,6cyclictest121rcu_preempt19:40:006
12755991810,6cyclictest121rcu_preempt19:30:166
12755991810,6cyclictest121rcu_preempt00:30:596
12755991810,5cyclictest121rcu_preempt20:19:366
12755991810,3cyclictest121rcu_preempt00:00:056
12754991814,1cyclictest16136-21nscd00:10:385
12749991817,1cyclictest1706-21sendmail-mta19:15:170
932521710,0sleep30-21swapper/322:37:293
232052179,0sleep10-21swapper/122:13:021
12755991710,5cyclictest121rcu_preempt20:05:126
12755991710,5cyclictest121rcu_preempt19:45:176
12755991710,5cyclictest121rcu_preempt19:20:136
12754991717,0cyclictest0-21swapper/523:33:335
12754991712,2cyclictest14757-21nscd23:12:095
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional