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2021-09-17 - 22:02

Intel(R) Xeon(R) CPU E3-1578L v5 @ 2.00GHz, Linux 4.19.1-rt3 (Profile)

Latency plot of system in rack #5, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot3.osadl.org (updated Fri Sep 17, 2021 12:49:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
23147992210,10cyclictest0-21swapper/510:12:365
23106992222,0cyclictest0-21swapper/112:06:591
23106992210,9cyclictest0-21swapper/112:30:151
23106992210,9cyclictest0-21swapper/111:55:441
23106992210,5cyclictest0-21swapper/111:51:171
23097992222,0cyclictest0-21swapper/010:15:180
23147992115,5cyclictest21918-21ssh11:57:185
23147992112,6cyclictest121rcu_preempt09:12:545
23147992111,8cyclictest121rcu_preempt09:55:125
23147992111,7cyclictest121rcu_preempt11:19:035
23147992110,8cyclictest0-21swapper/511:25:465
23147992110,8cyclictest0-21swapper/508:45:165
23106992110,9cyclictest0-21swapper/111:48:261
23106992110,9cyclictest0-21swapper/107:18:241
23106992110,8cyclictest0-21swapper/112:26:421
23106992110,8cyclictest0-21swapper/112:20:541
23106992110,8cyclictest0-21swapper/112:15:091
23106992110,8cyclictest0-21swapper/112:11:211
23106992110,8cyclictest0-21swapper/111:20:241
23106992110,8cyclictest0-21swapper/111:18:281
23106992110,8cyclictest0-21swapper/111:11:531
23106992110,8cyclictest0-21swapper/111:03:271
23106992110,8cyclictest0-21swapper/110:55:361
23106992110,8cyclictest0-21swapper/110:51:161
23106992110,8cyclictest0-21swapper/110:37:251
23106992110,8cyclictest0-21swapper/110:10:331
23106992110,8cyclictest0-21swapper/109:54:151
23106992110,8cyclictest0-21swapper/109:45:121
23106992110,8cyclictest0-21swapper/109:35:261
23106992110,8cyclictest0-21swapper/109:30:111
23106992110,8cyclictest0-21swapper/109:23:391
23106992110,8cyclictest0-21swapper/108:20:141
23106992110,7cyclictest0-21swapper/108:43:431
23106992110,7cyclictest0-21swapper/108:30:171
23147992011,7cyclictest121rcu_preempt11:40:275
23147992011,7cyclictest121rcu_preempt11:20:465
23147992011,7cyclictest121rcu_preempt10:26:285
23147992011,6cyclictest121rcu_preempt12:28:075
23147992011,6cyclictest121rcu_preempt09:50:155
23147992011,6cyclictest121rcu_preempt07:15:265
23147992010,8cyclictest0-21swapper/512:30:145
23147992010,8cyclictest0-21swapper/512:04:055
23147992010,8cyclictest0-21swapper/511:46:005
23147992010,8cyclictest0-21swapper/510:43:255
23147992010,8cyclictest0-21swapper/510:05:405
23147992010,8cyclictest0-21swapper/509:40:585
23147992010,8cyclictest0-21swapper/509:30:005
23147992010,8cyclictest0-21swapper/509:18:545
23147992010,8cyclictest0-21swapper/508:40:245
23147992010,8cyclictest0-21swapper/507:10:215
23147992010,7cyclictest1833-21sh12:05:075
23147992010,7cyclictest0-21swapper/512:35:245
23147992010,7cyclictest0-21swapper/512:20:125
23147992010,7cyclictest0-21swapper/512:15:305
23147992010,7cyclictest0-21swapper/512:10:385
23147992010,7cyclictest0-21swapper/511:50:295
23147992010,7cyclictest0-21swapper/511:10:205
23147992010,7cyclictest0-21swapper/511:05:205
23147992010,7cyclictest0-21swapper/510:55:175
23147992010,7cyclictest0-21swapper/510:45:255
23147992010,7cyclictest0-21swapper/510:24:065
23147992010,7cyclictest0-21swapper/510:15:165
23147992010,7cyclictest0-21swapper/510:00:175
23147992010,7cyclictest0-21swapper/509:45:305
23147992010,7cyclictest0-21swapper/509:33:205
23147992010,7cyclictest0-21swapper/509:05:275
23147992010,7cyclictest0-21swapper/508:55:265
23147992010,7cyclictest0-21swapper/508:00:165
23147992010,7cyclictest0-21swapper/507:55:145
23147992010,7cyclictest0-21swapper/507:30:185
23147992010,7cyclictest0-21swapper/507:20:205
23147992010,6cyclictest0-21swapper/509:20:155
23126992020,0cyclictest0-21swapper/311:44:333
23106992010,8cyclictest0-21swapper/109:25:101
23106992010,8cyclictest0-21swapper/107:20:221
23106992010,7cyclictest0-21swapper/112:35:261
23106992010,7cyclictest0-21swapper/112:00:101
23106992010,7cyclictest0-21swapper/111:40:201
23106992010,7cyclictest0-21swapper/111:35:261
23106992010,7cyclictest0-21swapper/111:30:151
23106992010,7cyclictest0-21swapper/111:25:201
23106992010,7cyclictest0-21swapper/111:07:091
23106992010,7cyclictest0-21swapper/110:45:101
23106992010,7cyclictest0-21swapper/110:40:031
23106992010,7cyclictest0-21swapper/110:30:181
23106992010,7cyclictest0-21swapper/110:25:401
23106992010,7cyclictest0-21swapper/110:20:121
23106992010,7cyclictest0-21swapper/110:15:271
23106992010,7cyclictest0-21swapper/110:07:071
23106992010,7cyclictest0-21swapper/110:00:191
23106992010,7cyclictest0-21swapper/109:55:141
23106992010,7cyclictest0-21swapper/109:40:171
23106992010,7cyclictest0-21swapper/109:15:371
23106992010,7cyclictest0-21swapper/109:11:201
23106992010,7cyclictest0-21swapper/109:05:251
23106992010,7cyclictest0-21swapper/108:45:241
23106992010,7cyclictest0-21swapper/107:55:241
23106992010,7cyclictest0-21swapper/107:50:161
23106992010,7cyclictest0-21swapper/107:45:251
23170991919,0cyclictest0-21swapper/710:32:267
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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