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2022-01-26 - 06:50

Intel(R) Xeon(R) CPU E3-1578L v5 @ 2.00GHz, Linux 4.19.1-rt3 (Profile)

Latency plot of system in rack #5, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot3.osadl.org (updated Wed Jan 26, 2022 00:50:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19403993737,0cyclictest0-21swapper/423:40:254
19403992910,12cyclictest0-21swapper/421:00:264
19403992424,0cyclictest0-21swapper/423:58:404
19406992310,10cyclictest0-21swapper/721:05:187
1940699230,22cyclictest0-21swapper/723:40:297
19403992210,9cyclictest0-21swapper/400:38:584
19403992210,10cyclictest0-21swapper/422:51:284
19403992110,8cyclictest18974-21mailstats20:05:294
19403992110,8cyclictest0-21swapper/423:15:294
19403992110,5cyclictest0-21swapper/419:30:004
19405992010,8cyclictest0-21swapper/600:21:226
19403992010,8cyclictest8543-21ssh22:35:394
19403992010,8cyclictest0-21swapper/423:32:494
19403992010,8cyclictest0-21swapper/422:00:064
19403992010,8cyclictest0-21swapper/419:35:004
19403992010,8cyclictest0-21swapper/400:31:234
19403992010,8cyclictest0-21swapper/400:25:204
19403992010,8cyclictest0-21swapper/400:20:264
19403992010,8cyclictest0-21swapper/400:15:204
19403992010,8cyclictest0-21swapper/400:03:564
19403992010,7cyclictest0-21swapper/422:21:534
19403992010,7cyclictest0-21swapper/420:20:164
19402992019,1cyclictest401ktimersoftd/323:59:363
19405991910,8cyclictest0-21swapper/600:30:496
19405991910,6cyclictest0-21swapper/621:45:276
19404991919,0cyclictest23171-21ls23:40:295
19403991910,8cyclictest0-21swapper/422:40:044
19403991910,8cyclictest0-21swapper/420:40:264
19403991910,7cyclictest0-21swapper/423:50:154
19403991910,7cyclictest0-21swapper/423:25:064
19403991910,7cyclictest0-21swapper/423:20:564
19403991910,7cyclictest0-21swapper/423:11:234
19403991910,7cyclictest0-21swapper/423:00:084
19403991910,7cyclictest0-21swapper/422:55:134
19403991910,7cyclictest0-21swapper/422:45:544
19403991910,7cyclictest0-21swapper/422:31:244
19403991910,7cyclictest0-21swapper/422:15:134
19403991910,7cyclictest0-21swapper/422:10:204
19403991910,7cyclictest0-21swapper/422:05:014
19403991910,7cyclictest0-21swapper/421:55:224
19403991910,7cyclictest0-21swapper/421:54:444
19403991910,7cyclictest0-21swapper/421:45:564
19403991910,7cyclictest0-21swapper/421:40:164
19403991910,7cyclictest0-21swapper/421:35:254
19403991910,7cyclictest0-21swapper/421:33:094
19403991910,7cyclictest0-21swapper/421:25:054
19403991910,7cyclictest0-21swapper/421:20:354
19403991910,7cyclictest0-21swapper/421:15:494
19403991910,7cyclictest0-21swapper/421:10:314
19403991910,7cyclictest0-21swapper/420:45:244
19403991910,7cyclictest0-21swapper/420:39:304
19403991910,7cyclictest0-21swapper/420:25:224
19403991910,7cyclictest0-21swapper/420:15:204
19403991910,7cyclictest0-21swapper/419:55:214
19403991910,7cyclictest0-21swapper/419:40:264
19403991910,7cyclictest0-21swapper/419:40:264
19403991910,7cyclictest0-21swapper/419:35:184
19403991910,7cyclictest0-21swapper/419:15:014
19403991910,7cyclictest0-21swapper/400:10:094
19403991910,7cyclictest0-21swapper/400:06:184
19403991910,6cyclictest0-21swapper/423:45:164
19403991910,6cyclictest0-21swapper/423:36:394
19403991910,6cyclictest0-21swapper/423:06:044
19403991910,6cyclictest0-21swapper/422:25:254
19403991910,6cyclictest0-21swapper/420:00:214
19400991910,9cyclictest0-21swapper/122:56:241
19405991810,6cyclictest0-21swapper/600:06:186
19403991810,7cyclictest0-21swapper/419:20:184
19403991810,6cyclictest0-21swapper/421:05:244
19403991810,6cyclictest0-21swapper/420:55:214
19403991810,6cyclictest0-21swapper/420:50:314
19403991810,6cyclictest0-21swapper/420:30:184
19403991810,6cyclictest0-21swapper/420:10:154
19403991810,6cyclictest0-21swapper/419:50:204
19403991810,6cyclictest0-21swapper/419:45:174
19403991810,6cyclictest0-21swapper/419:10:214
19402991818,0cyclictest0-21swapper/323:40:293
19402991815,3cyclictest3289-1kworker/3:0H21:59:453
19401991810,7cyclictest0-21swapper/221:05:182
19401991810,5cyclictest0-21swapper/200:13:442
19400991815,1cyclictest11911-21nscd21:30:301
19406991714,1cyclictest15846-21diskmemload00:15:177
19406991710,4cyclictest0-21swapper/721:00:297
19405991715,1cyclictest1135-21snmpd00:13:506
19405991710,6cyclictest0-21swapper/623:22:266
19405991710,6cyclictest0-21swapper/622:23:386
19404991715,1cyclictest731-21ptp4l00:39:475
19404991715,1cyclictest28356-21ssh21:33:125
19401991716,1cyclictest26974-21ssh23:43:232
19401991710,7cyclictest0-21swapper/200:26:312
19401991710,5cyclictest0-21swapper/221:00:272
19400991710,7cyclictest0-21swapper/123:30:021
19406991610,3cyclictest0-21swapper/721:45:167
19406991610,0cyclictest0-21swapper/700:04:097
19405991614,1cyclictest22666-21cut23:40:256
19405991610,4cyclictest0-21swapper/621:00:286
19405991610,0cyclictest0-21swapper/623:16:156
19404991615,1cyclictest15190-21ssh23:17:325
19404991610,6cyclictest0-21swapper/521:20:355
19404991610,6cyclictest0-21swapper/520:45:245
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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