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2023-01-27 - 15:02

x86 Intel Xeon i3-1578L v5 @2000 MHz, Linux 4.19.246-rt110 (Profile)

Latency plot of system in rack #5, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100, Linux 4.9.20-rt16, x86_64 highest latencies:
System rack5slot3.osadl.org (updated Fri Jan 27, 2023 12:50:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5335994746,0cyclictest0-21swapper/008:05:180
5346994646,0cyclictest0-21swapper/408:50:134
534699410,40cyclictest0-21swapper/407:20:164
5344994039,0cyclictest0-21swapper/207:15:192
5349993938,0cyclictest0-21swapper/709:50:167
5344993836,1cyclictest16751-21apt-get10:35:172
5349993030,0cyclictest0-21swapper/709:05:237
5349992928,1cyclictest0-21swapper/709:45:257
5345992929,0cyclictest0-21swapper/308:25:163
5346992828,0cyclictest14181-21apt-get07:25:144
5345992828,0cyclictest0-21swapper/308:30:313
5349992727,0cyclictest0-21swapper/708:50:217
5349992727,0cyclictest0-21swapper/707:10:027
5348992727,0cyclictest0-21swapper/608:40:206
5347992626,0cyclictest0-21swapper/508:00:145
5346992626,0cyclictest0-21swapper/409:45:214
5345992611,5cyclictest0-21swapper/309:00:183
5341992626,0cyclictest0-21swapper/112:38:121
5341992625,0cyclictest0-21swapper/109:50:151
5349992525,0cyclictest0-21swapper/708:05:187
5335992525,0cyclictest0-21swapper/008:00:140
534899240,3cyclictest0-21swapper/608:25:276
5347992424,0cyclictest0-21swapper/507:10:135
5346992424,0cyclictest0-21swapper/407:54:404
5345992424,0cyclictest0-21swapper/308:22:273
5344992424,0cyclictest0-21swapper/210:30:242
5349992323,0cyclictest0-21swapper/710:45:307
5349992310,5cyclictest0-21swapper/709:00:187
5347992323,0cyclictest0-21swapper/508:55:155
5347992310,5cyclictest0-21swapper/508:35:285
5346992323,0cyclictest0-21swapper/408:05:234
5345992323,0cyclictest0-21swapper/308:55:023
5344992323,0cyclictest0-21swapper/210:20:302
5335992323,0cyclictest0-21swapper/007:10:130
5335992310,3cyclictest0-21swapper/007:20:290
5348992222,0cyclictest0-21swapper/607:35:236
5345992222,0cyclictest0-21swapper/309:45:253
5335992222,0cyclictest0-21swapper/008:55:150
5349992110,5cyclictest0-21swapper/708:55:017
5348992121,0cyclictest0-21swapper/608:10:226
5346992115,5cyclictest996-21snmpd12:16:164
5346992115,5cyclictest996-21snmpd12:16:164
5344992110,3cyclictest0-21swapper/207:10:182
5341992110,4cyclictest0-21swapper/108:00:141
5341992110,3cyclictest0-21swapper/107:45:231
5341992110,11cyclictest0-21swapper/107:36:521
5349992010,3cyclictest0-21swapper/708:00:187
534999200,7cyclictest0-21swapper/707:15:357
5348992010,3cyclictest0-21swapper/607:55:246
5348992010,3cyclictest0-21swapper/607:55:246
5347992020,0cyclictest76350irq/125-eth010:33:245
5347992020,0cyclictest76350irq/125-eth008:25:555
5346992010,6cyclictest0-21swapper/408:29:334
5346992010,6cyclictest0-21swapper/408:00:244
5346992010,5cyclictest0-21swapper/408:20:424
5345992020,0cyclictest0-21swapper/307:35:193
5341992019,0cyclictest0-21swapper/108:36:371
5341992019,0cyclictest0-21swapper/107:56:401
5341992019,0cyclictest0-21swapper/107:56:401
5335992020,0cyclictest0-21swapper/008:35:230
5335992010,3cyclictest0-21swapper/007:15:010
5335992010,0cyclictest0-21swapper/009:00:180
534999193,10cyclictest3227-21kworker/7:107:30:247
5348991910,3cyclictest0-21swapper/608:30:026
5348991910,3cyclictest0-21swapper/607:30:236
5347991910,7cyclictest0-21swapper/509:46:565
5347991910,6cyclictest0-21swapper/507:15:015
5347991910,2cyclictest0-21swapper/507:30:245
5346991919,0cyclictest0-21swapper/407:19:354
5346991910,3cyclictest0-21swapper/410:34:194
5346991910,2cyclictest0-21swapper/408:55:014
5345991919,0cyclictest0-21swapper/311:26:063
5345991913,6cyclictest996-21snmpd09:25:023
5345991910,4cyclictest0-21swapper/307:20:233
5345991910,3cyclictest0-21swapper/308:15:163
5345991910,3cyclictest0-21swapper/308:00:233
5345991910,2cyclictest0-21swapper/307:50:303
5344991910,5cyclictest0-21swapper/208:30:142
5344991910,2cyclictest0-21swapper/209:45:252
5341991919,0cyclictest0-21swapper/111:43:291
5341991918,1cyclictest0-21swapper/112:18:531
5341991918,1cyclictest0-21swapper/112:18:531
5341991910,9cyclictest0-21swapper/107:12:031
5341991910,4cyclictest0-21swapper/107:15:351
5341991910,2cyclictest0-21swapper/108:30:141
5341991910,0cyclictest0-21swapper/107:22:051
533599190,13cyclictest0-21swapper/009:50:160
533599190,0cyclictest0-21swapper/010:56:290
5349991810,3cyclictest0-21swapper/708:20:437
5349991810,3cyclictest0-21swapper/707:55:237
5349991810,3cyclictest0-21swapper/707:55:237
5349991810,2cyclictest0-21swapper/707:20:167
5348991813,5cyclictest725-21ptp4l09:48:546
5347991818,0cyclictest76350irq/125-eth007:35:295
5347991810,3cyclictest0-21swapper/507:55:145
5347991810,3cyclictest0-21swapper/507:55:145
5347991810,3cyclictest0-21swapper/507:20:285
5346991810,5cyclictest0-21swapper/408:47:284
5346991810,3cyclictest0-21swapper/407:40:154
5346991810,3cyclictest0-21swapper/407:30:244
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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