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2022-08-11 - 16:12

x86 Intel Xeon i3-1578L v5 @2000 MHz, Linux 4.19.246-rt110 (Profile)

Latency plot of system in rack #5, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100, highest latencies:
System rack5slot3.osadl.org (updated Thu Aug 11, 2022 12:49:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9424995510,0cyclictest0-21swapper/209:05:202
9428995049,0cyclictest0-21swapper/608:35:126
9429994710,37cyclictest0-21swapper/709:10:287
9424994442,1cyclictest321ktimersoftd/211:45:122
9423994343,0cyclictest0-21swapper/111:25:181
9429994141,0cyclictest0-21swapper/707:10:147
9426994135,5cyclictest30986-21needreboot07:45:184
9429993939,0cyclictest0-21swapper/711:25:187
942699390,39cyclictest0-21swapper/407:30:224
9422993937,1cyclictest0-21swapper/009:05:210
9426993736,0cyclictest0-21swapper/408:46:434
9429993636,0cyclictest0-21swapper/707:50:127
9427993634,1cyclictest23614-21apt-get08:35:125
9427993610,0cyclictest0-21swapper/509:00:205
9424993636,0cyclictest0-21swapper/211:30:012
9428993535,0cyclictest0-21swapper/612:35:226
9424993330,2cyclictest1220-21uname07:50:172
9424993231,0cyclictest0-21swapper/208:50:122
9422993231,0cyclictest0-21swapper/008:40:120
9425993131,0cyclictest0-21swapper/309:10:233
9424993131,0cyclictest0-21swapper/212:34:462
9425993030,0cyclictest0-21swapper/312:35:223
9428992928,0cyclictest0-21swapper/609:10:276
9427992929,0cyclictest0-21swapper/508:10:175
9424992929,0cyclictest0-21swapper/208:30:192
9423992929,0cyclictest0-21swapper/111:35:231
9423992910,3cyclictest0-21swapper/108:35:011
9422992929,0cyclictest0-21swapper/011:03:250
9422992910,6cyclictest0-21swapper/008:10:210
9428992810,3cyclictest0-21swapper/607:30:186
9427992828,0cyclictest76350irq/125-eth011:41:285
9426992828,0cyclictest0-21swapper/411:20:014
9426992810,9cyclictest0-21swapper/408:10:214
9423992810,3cyclictest0-21swapper/108:35:211
9422992810,4cyclictest0-21swapper/008:46:430
9423992721,5cyclictest30985-21uname07:45:191
9426992625,0cyclictest0-21swapper/409:05:134
9424992626,0cyclictest0-21swapper/207:40:242
9423992626,0cyclictest0-21swapper/107:30:221
9429992525,0cyclictest0-21swapper/711:35:227
9429992523,1cyclictest0-21swapper/707:30:227
9429992510,5cyclictest0-21swapper/708:50:227
9425992525,0cyclictest0-21swapper/311:35:183
9423992525,0cyclictest0-21swapper/111:03:511
9422992510,15cyclictest0-21swapper/012:10:380
9429992410,5cyclictest0-21swapper/709:05:277
9429992410,4cyclictest0-21swapper/707:25:307
9428992424,0cyclictest0-21swapper/611:01:426
9427992419,5cyclictest0-21swapper/511:20:005
9424992410,4cyclictest0-21swapper/211:15:232
9427992323,0cyclictest76350irq/125-eth011:26:445
9427992310,2cyclictest0-21swapper/507:45:245
9427992310,11cyclictest0-21swapper/507:30:015
9427992310,0cyclictest0-21swapper/507:35:235
9423992310,0cyclictest0-21swapper/111:42:301
9422992316,2cyclictest6205-21nscd12:18:540
9429992221,1cyclictest0-21swapper/709:54:287
9429992221,0cyclictest0-21swapper/707:45:017
9428992221,1cyclictest0-21swapper/612:09:166
9428992210,5cyclictest0-21swapper/611:20:016
9428992210,4cyclictest0-21swapper/608:10:226
942899220,4cyclictest0-21swapper/607:40:276
9427992210,5cyclictest0-21swapper/511:30:165
9425992210,4cyclictest0-21swapper/309:00:013
9422992222,0cyclictest0-21swapper/011:45:130
9422992221,0cyclictest0-21swapper/011:15:180
9422992210,4cyclictest0-21swapper/009:10:270
9429992118,3cyclictest0-21swapper/712:00:597
9429992110,4cyclictest0-21swapper/709:00:257
9428992120,1cyclictest0-21swapper/609:05:206
9426992110,5cyclictest0-21swapper/408:30:224
9425992110,7cyclictest0-21swapper/307:45:003
9425992110,5cyclictest0-21swapper/308:35:203
9424992120,1cyclictest0-21swapper/207:35:152
9424992120,0cyclictest0-21swapper/208:46:442
9423992121,0cyclictest0-21swapper/108:46:431
9423992110,5cyclictest0-21swapper/111:05:131
9423992110,2cyclictest0-21swapper/107:50:231
9428992019,1cyclictest641ktimersoftd/611:42:356
9427992020,0cyclictest11896-21strings09:10:225
9427992020,0cyclictest0-21swapper/512:35:225
9427992010,1cyclictest0-21swapper/511:15:225
9426992010,4cyclictest0-21swapper/408:35:114
9426992010,3cyclictest0-21swapper/411:25:394
9426992010,2cyclictest0-21swapper/411:41:284
9426992010,2cyclictest0-21swapper/411:18:164
9425992014,6cyclictest725-21ptp4l11:18:303
9425992010,2cyclictest0-21swapper/307:30:173
9424992012,3cyclictest321ktimersoftd/208:15:102
9424992010,4cyclictest0-21swapper/208:10:222
9423992018,2cyclictest0-21swapper/107:19:421
9422992010,6cyclictest0-21swapper/007:10:190
942299200,20cyclictest0-21swapper/007:15:210
9429991913,5cyclictest0-21swapper/708:05:027
9429991910,0cyclictest0-21swapper/711:15:517
9427991919,0cyclictest76350irq/125-eth009:50:185
9427991918,0cyclictest76350irq/125-eth008:59:275
9426991910,3cyclictest0-21swapper/408:50:234
9426991910,3cyclictest0-21swapper/407:25:294
9425991910,2cyclictest0-21swapper/311:41:433
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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