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2022-11-29 - 18:25

x86 Intel Xeon i3-1578L v5 @2000 MHz, Linux 4.19.246-rt110 (Profile)

Latency plot of system in rack #5, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100, highest latencies:
System rack5slot3.osadl.org (updated Tue Nov 29, 2022 12:50:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20753994645,0cyclictest0-21swapper/307:45:133
20757994545,0cyclictest0-21swapper/708:00:197
20754994443,1cyclictest0-21swapper/410:35:244
20751994341,1cyclictest0-21swapper/107:45:171
20747994343,0cyclictest0-21swapper/008:00:180
20752994040,0cyclictest0-21swapper/207:15:132
20747993938,0cyclictest0-21swapper/007:50:190
20751993810,28cyclictest0-21swapper/107:40:011
20751993735,1cyclictest0-21swapper/107:25:131
20751993634,1cyclictest0-21swapper/108:05:171
20751993610,25cyclictest0-21swapper/112:25:211
20757993434,0cyclictest0-21swapper/708:30:167
20757993434,0cyclictest0-21swapper/708:30:167
20751993410,24cyclictest0-21swapper/107:15:001
20751993310,22cyclictest0-21swapper/108:40:131
20751993310,21cyclictest0-21swapper/107:55:201
20751993210,20cyclictest0-21swapper/107:20:331
20751993210,18cyclictest0-21swapper/108:00:231
20755993112,13cyclictest76350irq/125-eth010:35:285
20751993110,20cyclictest0-21swapper/107:10:201
20756993030,0cyclictest0-21swapper/607:10:016
20755993029,1cyclictest0-21swapper/507:45:175
20751993010,19cyclictest0-21swapper/108:35:301
20751993010,18cyclictest0-21swapper/110:40:261
20751993010,15cyclictest0-21swapper/109:26:201
20751993010,15cyclictest0-21swapper/109:26:191
20751993010,14cyclictest0-21swapper/107:50:331
20757992929,0cyclictest0-21swapper/708:10:157
20752992929,0cyclictest0-21swapper/208:00:132
20752992928,0cyclictest0-21swapper/209:25:222
20752992928,0cyclictest0-21swapper/209:25:222
20751992913,14cyclictest121rcu_preempt08:10:091
20747992929,0cyclictest0-21swapper/012:34:140
20747992827,0cyclictest0-21swapper/008:10:140
20757992725,1cyclictest0-21swapper/707:45:187
20756992727,0cyclictest0-21swapper/608:00:196
20755992721,5cyclictest0-21swapper/507:15:005
20751992710,12cyclictest0-21swapper/109:55:291
2074799279,14cyclictest9-21ksoftirqd/007:45:000
20757992610,4cyclictest0-21swapper/707:20:297
20757992610,11cyclictest721ktimersoftd/707:45:017
20757992610,10cyclictest0-21swapper/709:27:517
20757992610,10cyclictest0-21swapper/709:27:517
2075599269,13cyclictest57-21ksoftirqd/507:55:205
20753992626,0cyclictest0-21swapper/308:54:223
20753992610,5cyclictest0-21swapper/308:15:123
20752992626,0cyclictest0-21swapper/209:55:292
20751992610,15cyclictest0-21swapper/110:35:251
20757992523,2cyclictest0-21swapper/711:11:237
20756992525,0cyclictest0-21swapper/607:35:216
2075599256,13cyclictest561ktimersoftd/508:10:145
20755992523,1cyclictest0-21swapper/508:05:175
20755992510,3cyclictest561ktimersoftd/507:45:005
20752992510,6cyclictest0-21swapper/208:05:162
2075299250,0cyclictest0-21swapper/208:35:162
20751992510,12cyclictest121rcu_preempt11:26:061
20751992510,12cyclictest121rcu_preempt10:48:471
20751992510,12cyclictest121rcu_preempt09:41:121
20747992524,1cyclictest0-21swapper/007:45:180
2075799246,6cyclictest0-21swapper/710:35:287
20756992423,1cyclictest4551-21apt-get08:40:136
20755992424,0cyclictest0-21swapper/510:25:015
20755992410,6cyclictest0-21swapper/508:50:235
20751992411,10cyclictest121rcu_preempt11:44:181
20751992410,8cyclictest121rcu_preempt12:13:551
20751992410,12cyclictest121rcu_preempt08:15:161
20751992410,12cyclictest0-21swapper/111:15:381
20751992410,12cyclictest0-21swapper/111:15:381
20751992410,11cyclictest121rcu_preempt10:25:151
20751992410,11cyclictest121rcu_preempt09:36:521
20751992410,11cyclictest121rcu_preempt09:32:521
20756992310,4cyclictest0-21swapper/607:20:346
20755992323,0cyclictest0-21swapper/512:25:195
20755992323,0cyclictest0-21swapper/507:25:135
20754992310,5cyclictest0-21swapper/407:35:254
20753992323,0cyclictest20080-21diskmemload11:20:133
20751992311,5cyclictest121rcu_preempt12:22:241
20751992310,12cyclictest0-21swapper/108:50:221
20751992310,11cyclictest121rcu_preempt10:55:111
20751992310,11cyclictest121rcu_preempt09:18:281
20751992310,11cyclictest0-21swapper/112:31:191
20751992310,10cyclictest121rcu_preempt10:32:241
2075199230,5cyclictest0-21swapper/111:20:101
20757992220,1cyclictest0-21swapper/707:25:137
20756992222,0cyclictest0-21swapper/607:50:196
2075599229,12cyclictest0-21swapper/507:15:015
20755992214,7cyclictest561ktimersoftd/508:45:125
20755992213,6cyclictest57-21ksoftirqd/511:18:285
20755992213,6cyclictest57-21ksoftirqd/511:18:285
20755992213,3cyclictest561ktimersoftd/507:50:285
20754992210,4cyclictest0-21swapper/408:30:224
20754992210,4cyclictest0-21swapper/408:30:224
20752992221,1cyclictest21038-21apt-get08:10:142
20752992210,6cyclictest0-21swapper/207:45:202
2075199222,19cyclictest0-21swapper/107:40:211
20751992211,9cyclictest121rcu_preempt09:06:511
20751992211,5cyclictest121rcu_preempt11:47:441
20751992211,5cyclictest121rcu_preempt11:47:441
20751992210,9cyclictest0-21swapper/109:51:161
20751992210,9cyclictest0-21swapper/108:24:241
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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