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2019-07-16 - 02:51

Intel(R) Xeon(R) CPU E3-1578L v5 @ 2.00GHz, Linux 4.19.1-rt3 (Profile)

Latency plot of system in rack #5, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot3.osadl.org (updated Tue Jul 16, 2019 00:49:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5442992828,0cyclictest0-21swapper/000:05:090
5444992510,0cyclictest0-21swapper/221:15:082
547399231,9cyclictest0-21swapper/700:10:037
5464992222,0cyclictest74050irq/127-eth021:17:326
5464992210,4cyclictest0-21swapper/600:10:036
544699211,9cyclictest0-21swapper/400:10:034
5464992010,5cyclictest0-21swapper/621:25:036
5464992010,2cyclictest0-21swapper/621:20:036
5443992019,0cyclictest0-21swapper/121:25:031
5444991910,3cyclictest0-21swapper/221:25:032
5444991910,3cyclictest0-21swapper/221:20:032
5445991810,3cyclictest0-21swapper/300:10:033
547399172,8cyclictest73-21ksoftirqd/700:10:017
5473991716,0cyclictest0-21swapper/721:25:047
5464991717,0cyclictest20672-21strings23:40:106
5464991710,4cyclictest0-21swapper/619:45:036
5454991717,0cyclictest0-21swapper/521:19:285
5445991717,0cyclictest0-21swapper/321:20:093
5445991710,3cyclictest0-21swapper/320:30:023
5443991710,2cyclictest0-21swapper/121:20:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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