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2024-07-27 - 07:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot3.osadl.org (updated Sat Jul 27, 2024 00:50:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
217122870,0sleep2311rcuc/220:45:112
2750428350,29sleep70-21swapper/719:09:087
2739528350,29sleep10-21swapper/119:07:351
2740928147,29sleep60-21swapper/619:07:476
2756627945,29sleep20-21swapper/219:09:592
2755627844,30sleep30-21swapper/319:09:533
2754827845,28sleep40-21swapper/419:09:464
2732527743,29sleep50-21swapper/519:06:345
2669027543,26sleep00-21swapper/019:05:250
287262500,0sleep00-21swapper/022:54:540
261592500,0sleep60-21swapper/620:50:196
261592500,0sleep60-21swapper/620:50:186
62712460,0sleep70-21swapper/722:28:127
90592440,0sleep10-21swapper/121:42:581
186582440,0sleep30-21swapper/323:51:433
28001991615,1cyclictest31554-21ssh21:22:394
28000991610,6cyclictest73550irq/125-eth023:35:473
27997991610,6cyclictest0-21swapper/023:26:020
27997991610,6cyclictest0-21swapper/022:20:150
28004991510,5cyclictest0-21swapper/700:30:047
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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