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2026-06-06 - 16:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot3.osadl.org (updated Sat Jun 06, 2026 00:56:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
929299831110,83cyclictest9286-21cyclictest00:28:484
928999672203,296cyclictest0-21swapper/122:06:131
92929966730,127cyclictest0-21swapper/422:28:464
928999667156,296cyclictest0-21swapper/100:07:381
92929965965,591cyclictest0-21swapper/400:22:334
92919965198,380cyclictest0-21swapper/322:04:203
92899963884,380cyclictest0-21swapper/122:52:061
929599637171,84cyclictest121rcu_preempt22:05:037
92909963582,380cyclictest0-21swapper/222:10:342
92919963279,296cyclictest0-21swapper/322:06:273
929299630120,507cyclictest23186-21ssh23:48:594
929499629245,126cyclictest0-21swapper/600:27:556
92929962935,591cyclictest0-21swapper/422:20:194
92899962979,126cyclictest0-21swapper/120:09:521
92899962979,126cyclictest0-21swapper/120:09:521
929299628165,460cyclictest64450irq/122-eth023:23:114
929299624284,338cyclictest64450irq/122-eth000:42:344
92919962267,296cyclictest0-21swapper/300:43:463
928999622111,380cyclictest0-21swapper/121:49:451
92929961417,508cyclictest0-21swapper/400:09:444
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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