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2025-07-12 - 13:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot3.osadl.org (updated Sat Jul 12, 2025 00:50:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2466928541,39sleep50-21swapper/519:07:055
2467128249,29sleep70-21swapper/719:07:087
2485928047,29sleep60-21swapper/619:09:486
2480028037,38sleep30-21swapper/319:08:573
2347927846,26sleep10-21swapper/119:05:171
2460827743,30sleep20-21swapper/219:06:152
2472927643,29sleep00-21swapper/019:07:580
2481927440,29sleep40-21swapper/419:09:144
88802530,0sleep30-21swapper/321:45:173
290962500,0sleep00-21swapper/000:36:310
148682500,0sleep00-21swapper/023:09:130
148682500,0sleep00-21swapper/023:09:130
7072470,0sleep60-21swapper/620:15:126
25305994646,0cyclictest0-21swapper/119:10:101
326622450,0sleep50-21swapper/519:20:105
272812450,0sleep30-21swapper/322:59:233
205622440,0sleep30-21swapper/300:32:343
25311993838,0cyclictest0-21swapper/722:20:177
25311993535,0cyclictest0-21swapper/719:10:117
25309992828,0cyclictest0-21swapper/523:54:425
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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