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2024-06-14 - 15:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot3.osadl.org (updated Fri Jun 14, 2024 00:50:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3217029359,29sleep30-21swapper/319:05:283
3217029359,29sleep30-21swapper/319:05:283
34028450,29sleep70-21swapper/719:07:577
34028450,29sleep70-21swapper/719:07:577
37728268,9sleep50-21swapper/519:08:265
37728268,9sleep50-21swapper/519:08:265
45628046,29sleep40-21swapper/419:09:304
45628046,29sleep40-21swapper/419:09:304
30028047,29sleep60-21swapper/619:07:246
30028047,29sleep60-21swapper/619:07:246
46127933,41sleep00-21swapper/019:09:340
46127933,41sleep00-21swapper/019:09:330
36127642,29sleep10-21swapper/119:08:151
36127642,29sleep10-21swapper/119:08:141
47427440,30sleep20-21swapper/219:09:442
47427440,30sleep20-21swapper/219:09:442
175092560,0sleep70-21swapper/722:30:297
128322500,0sleep20-21swapper/200:33:542
300242480,0sleep70-21swapper/721:35:117
275652480,0sleep20-21swapper/221:18:262
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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