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2023-05-28 - 18:51

x86 Intel Xeon i3-1578L v5 @2000 MHz, Linux 4.19.246-rt110 (Profile)

Latency plot of system in rack #5, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot3.osadl.org (updated Sun May 28, 2023 12:50:19)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
51628348,30sleep30-21swapper/307:08:323
41328249,29sleep00-21swapper/007:07:100
46628046,30sleep40-21swapper/407:07:544
54427945,30sleep10-21swapper/107:08:541
48727945,30sleep70-21swapper/707:08:127
36727945,30sleep20-21swapper/207:06:302
32327844,30sleep60-21swapper/607:05:546
3184627874,2sleep50-21swapper/507:05:215
235712530,0sleep70-21swapper/709:17:267
311432470,0sleep70-21swapper/710:35:007
289832470,0sleep40-21swapper/409:56:314
28382440,0sleep20-21swapper/212:25:292
144952440,0sleep40-21swapper/407:30:194
309562390,0sleep30-21swapper/312:23:533
1099993632,4cyclictest0-21swapper/610:35:286
1095992929,0cyclictest0-21swapper/211:05:172
1098992423,1cyclictest776-21gmain11:51:335
109899240,0cyclictest0-21swapper/507:10:015
1100992323,0cyclictest0-21swapper/711:02:187
1100992114,7cyclictest673-21cron09:48:017
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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