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2024-10-12 - 18:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot3.osadl.org (updated Sat Oct 12, 2024 12:50:14)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
794928652,29sleep10-21swapper/107:06:301
814728037,38sleep50-21swapper/507:09:235
799928045,29sleep60-21swapper/607:07:166
789928044,30sleep70-21swapper/707:05:477
793127641,31sleep30-21swapper/307:06:153
793927541,30sleep20-21swapper/207:06:232
789227338,30sleep00-21swapper/007:05:410
790527238,29sleep40-21swapper/407:05:524
199772550,0sleep10-21swapper/111:00:001
20152540,0sleep30-21swapper/311:53:273
236682500,0sleep70-21swapper/711:48:117
262412480,0sleep70-21swapper/709:45:137
155962460,0sleep30-21swapper/311:44:463
238712450,0sleep60-21swapper/609:59:446
8623993410,0cyclictest0-21swapper/112:14:501
8625993333,0cyclictest0-21swapper/307:10:123
8627992929,0cyclictest0-21swapper/509:28:465
8626992725,0cyclictest69450irq/124-eth009:28:354
8622992727,0cyclictest0-21swapper/009:30:120
8622992710,0cyclictest0-21swapper/011:23:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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