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2021-07-26 - 19:17

Intel(R) Xeon(R) CPU E3-1578L v5 @ 2.00GHz, Linux 4.19.1-rt3 (Profile)

Latency plot of system in rack #5, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot3.osadl.org (updated Mon Jul 26, 2021 12:50:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1473993512,22cyclictest0-21swapper/308:45:113
1473992210,10cyclictest0-21swapper/311:33:193
1473992210,10cyclictest0-21swapper/311:33:193
1492992110,4cyclictest0-21swapper/508:45:125
1473992121,0cyclictest0-21swapper/308:40:413
1473992110,9cyclictest0-21swapper/312:18:263
1473992110,9cyclictest0-21swapper/308:12:283
1473992110,8cyclictest0-21swapper/311:36:263
1473992110,7cyclictest0-21swapper/311:59:063
1473992010,8cyclictest0-21swapper/310:13:423
1473992010,8cyclictest0-21swapper/310:06:543
1473992010,8cyclictest0-21swapper/309:58:593
1473992010,8cyclictest0-21swapper/309:43:293
1473992010,8cyclictest0-21swapper/309:12:533
1473992010,6cyclictest0-21swapper/309:15:093
1473991910,8cyclictest0-21swapper/309:37:563
1473991910,6cyclictest0-21swapper/312:36:523
1473991910,6cyclictest0-21swapper/312:32:153
1473991910,6cyclictest0-21swapper/311:54:293
1473991910,6cyclictest0-21swapper/311:25:073
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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