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2022-06-29 - 15:03

x86 Intel Xeon i3-1578L v5 @2000 MHz, Linux 4.19.246-rt110 (Profile)

Latency plot of system in rack #5, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack5slot3.osadl.org (updated Wed Jun 29, 2022 12:50:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3491993937,1cyclictest0-21swapper/707:55:167
3447993636,0cyclictest0-21swapper/007:50:160
3447993636,0cyclictest0-21swapper/007:50:160
3456993510,0cyclictest0-21swapper/110:52:391
3468993332,0cyclictest0-21swapper/307:55:163
3464992828,0cyclictest0-21swapper/207:50:012
3464992828,0cyclictest0-21swapper/207:50:012
3456992626,0cyclictest0-21swapper/107:50:021
3456992626,0cyclictest0-21swapper/107:50:021
3491992510,7cyclictest0-21swapper/707:50:207
3491992510,7cyclictest0-21swapper/707:50:207
3486992525,0cyclictest0-21swapper/607:50:016
3486992525,0cyclictest0-21swapper/607:50:016
3468992423,0cyclictest0-21swapper/307:12:503
344799243,8cyclictest0-21swapper/007:40:000
3474992323,0cyclictest0-21swapper/407:45:164
3481992210,4cyclictest0-21swapper/508:00:225
3474992222,0cyclictest0-21swapper/408:00:104
3468992210,3cyclictest0-21swapper/307:50:203
3468992210,3cyclictest0-21swapper/307:50:203
345699220,0cyclictest0-21swapper/111:51:011
3486992010,2cyclictest0-21swapper/607:55:196
3474992019,0cyclictest0-21swapper/407:15:114
3474992019,0cyclictest0-21swapper/407:15:114
3486991910,3cyclictest0-21swapper/608:00:206
3481991910,1cyclictest0-21swapper/507:50:215
3481991910,1cyclictest0-21swapper/507:50:205
3474991919,0cyclictest0-21swapper/411:15:094
3474991918,0cyclictest0-21swapper/408:50:104
3474991910,4cyclictest0-21swapper/407:10:204
3464991910,3cyclictest0-21swapper/207:35:202
3456991917,2cyclictest720-21irqbalance12:19:531
3447991910,3cyclictest0-21swapper/008:50:110
3491991810,4cyclictest0-21swapper/708:00:207
3491991810,0cyclictest0-21swapper/707:45:207
3468991818,0cyclictest0-21swapper/312:29:463
3468991810,3cyclictest0-21swapper/307:15:003
3468991810,3cyclictest0-21swapper/307:15:003
3468991810,0cyclictest0-21swapper/308:00:213
3464991810,4cyclictest0-21swapper/208:00:192
3447991816,2cyclictest0-21swapper/012:07:030
3447991810,5cyclictest0-21swapper/008:00:210
3491991710,4cyclictest0-21swapper/707:35:197
3491991710,3cyclictest0-21swapper/708:45:277
3474991710,2cyclictest0-21swapper/408:45:274
3468991710,0cyclictest0-21swapper/311:44:273
3464991710,0cyclictest0-21swapper/211:00:172
3456991710,4cyclictest0-21swapper/107:12:491
3456991710,2cyclictest0-21swapper/107:55:191
3456991710,0cyclictest0-21swapper/112:25:281
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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