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2024-04-15 - 01:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack5slot3.osadl.org (updated Sat Apr 13, 2024 12:50:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1409529589,3sleep70-21swapper/707:05:237
18962880,0sleep70-21swapper/711:05:277
1579728046,29sleep20-21swapper/207:06:062
1579128046,30sleep50-21swapper/507:06:025
1576528047,29sleep60-21swapper/607:05:396
1591827843,30sleep00-21swapper/007:07:500
1588327843,30sleep30-21swapper/307:07:203
1347527340,29sleep10-21swapper/107:05:101
1347827237,30sleep40-21swapper/407:05:134
71142520,0sleep70-21swapper/712:04:287
192962490,0sleep10-21swapper/110:56:241
12132490,0sleep50-21swapper/512:37:415
12132490,0sleep50-21swapper/512:37:405
139032460,0sleep10-21swapper/109:21:211
151392420,0sleep00-21swapper/012:26:470
16503992310,11cyclictest121rcu_preempt11:22:383
16503992310,11cyclictest121rcu_preempt10:34:273
16503992310,11cyclictest121rcu_preempt09:50:103
16505992210,10cyclictest0-21swapper/510:52:515
16503992211,9cyclictest121rcu_preempt10:37:593
16503992210,9cyclictest121rcu_preempt12:21:033
16503992210,9cyclictest121rcu_preempt12:07:023
16503992210,10cyclictest121rcu_preempt12:12:223
16503992210,10cyclictest121rcu_preempt11:47:383
16505992110,11cyclictest121rcu_preempt08:49:395
16503992111,8cyclictest121rcu_preempt11:00:343
16503992111,8cyclictest121rcu_preempt10:43:103
16503992110,9cyclictest121rcu_preempt12:33:313
16503992110,9cyclictest121rcu_preempt10:21:073
16503992110,9cyclictest121rcu_preempt10:11:103
16503992110,8cyclictest0-21swapper/309:12:593
16503992110,10cyclictest121rcu_preempt11:32:193
16503992110,10cyclictest121rcu_preempt09:26:543
16505992011,7cyclictest121rcu_preempt10:25:195
16505992011,7cyclictest121rcu_preempt09:45:275
16505992011,6cyclictest131rcu_sched11:30:525
16505992010,8cyclictest121rcu_preempt11:12:565
16505992010,7cyclictest121rcu_preempt12:15:215
16505992010,7cyclictest121rcu_preempt10:35:255
16505992010,7cyclictest121rcu_preempt08:10:215
16505992010,6cyclictest121rcu_preempt09:45:005
16503992011,7cyclictest121rcu_preempt12:36:483
16503992011,7cyclictest121rcu_preempt12:36:473
16503992011,7cyclictest121rcu_preempt11:17:453
16503992011,7cyclictest121rcu_preempt08:40:193
16503992011,6cyclictest121rcu_preempt12:15:123
16503992011,6cyclictest121rcu_preempt12:00:263
16503992011,6cyclictest121rcu_preempt11:35:213
16503992011,6cyclictest121rcu_preempt11:05:363
16503992011,6cyclictest121rcu_preempt10:58:213
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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