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2025-05-24 - 11:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack5slot3.osadl.org (updated Sat May 24, 2025 00:50:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2185628844,28sleep30-21swapper/319:07:203
2201128450,30sleep70-21swapper/719:09:337
2193528451,29sleep60-21swapper/619:08:276
2201528147,29sleep20-21swapper/219:09:362
2181328147,29sleep50-21swapper/519:06:435
2193027944,30sleep10-21swapper/119:08:231
2178727742,30sleep00-21swapper/019:06:220
2193327641,30sleep40-21swapper/419:08:254
138572550,0sleep60-21swapper/622:50:216
43282540,0sleep40-21swapper/421:12:114
257672490,1sleep625761-21apt-config00:14:596
226282490,0sleep50-21swapper/522:55:085
112992480,0sleep70-21swapper/721:30:397
84682470,0sleep20-21swapper/222:00:292
40202460,0sleep30-21swapper/321:27:403
156322460,0sleep10-21swapper/123:22:271
40212450,0sleep10-21swapper/122:15:001
114612440,0sleep30-21swapper/300:39:063
111792440,0sleep30-21swapper/322:02:133
2204624138,1sleep30-21swapper/319:10:013
22476992727,0cyclictest0-21swapper/319:45:023
22475992510,13cyclictest121rcu_preempt00:28:002
22475992411,10cyclictest121rcu_preempt22:21:212
22475992410,13cyclictest121rcu_preempt23:58:092
22475992410,12cyclictest0-21swapper/200:15:582
22475992410,10cyclictest121rcu_preempt23:32:142
22475992311,10cyclictest121rcu_preempt22:16:572
22475992310,5cyclictest121rcu_preempt21:17:372
22475992310,10cyclictest121rcu_preempt23:54:212
22475992310,10cyclictest121rcu_preempt21:14:252
2247599223,17cyclictest0-21swapper/219:45:022
22475992216,4cyclictest121rcu_preempt00:23:022
22475992211,9cyclictest121rcu_preempt00:05:142
22475992211,8cyclictest121rcu_preempt21:31:302
22475992210,11cyclictest121rcu_preempt00:04:452
22475992210,10cyclictest121rcu_preempt22:07:542
22475992210,10cyclictest121rcu_preempt21:35:012
22480992121,0cyclictest0-21swapper/700:21:577
22476992110,8cyclictest0-21swapper/321:10:153
2247699210,17cyclictest24543-21turbostat.cron22:25:003
22475992114,5cyclictest131rcu_sched22:50:532
22475992111,8cyclictest121rcu_preempt23:10:452
22475992111,8cyclictest121rcu_preempt21:56:152
22475992111,8cyclictest121rcu_preempt19:50:212
22475992111,7cyclictest121rcu_preempt23:40:232
22475992111,7cyclictest121rcu_preempt22:30:152
22475992111,7cyclictest121rcu_preempt21:25:062
22475992111,7cyclictest121rcu_preempt19:25:202
22475992111,7cyclictest121rcu_preempt00:35:152
22475992111,7cyclictest121rcu_preempt00:30:172
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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