You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2024-05-25 - 07:02
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack5slot4.osadl.org (updated Sat May 25, 2024 00:44:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120942111101,7sleep30-21swapper/319:08:533
11847210996,8sleep00-21swapper/019:05:410
12068210898,7sleep20-21swapper/219:08:322
12117210797,7sleep10-21swapper/119:09:101
293682730,0sleep20-21swapper/223:05:312
61312720,1sleep26134-21kthreadcore22:20:232
247162660,1sleep3391ktimersoftd/323:20:263
132862620,0sleep00-21swapper/000:24:400
140112610,0sleep10-21swapper/119:35:181
315242600,0sleep20-21swapper/222:15:312
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional