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2026-05-11 - 17:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack5slot4.osadl.org (updated Mon May 11, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6108213980,7sleep00-21swapper/007:08:020
61242124115,6sleep10-21swapper/107:08:151
59402118108,7sleep20-21swapper/207:05:522
60962113103,7sleep30-21swapper/307:07:543
60292690,0sleep30-21swapper/310:25:203
295362660,1sleep30-21swapper/307:55:183
93152630,0sleep30-21swapper/309:05:153
71492560,1sleep07152-21kthreadcore07:35:170
107542560,0sleep30-21swapper/309:35:153
642099305,24cyclictest0-21swapper/108:55:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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