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2025-07-14 - 23:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack5slot4.osadl.org (updated Mon Jul 14, 2025 12:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14684211962,54sleep20-21swapper/207:07:182
146872113104,6sleep00-21swapper/007:07:200
145932112103,6sleep30-21swapper/307:06:073
147922111102,6sleep10-21swapper/107:08:411
306132650,1sleep330619-21kthreadcore08:40:223
257332620,0sleep30-21swapper/310:50:163
8262580,1sleep229-21rcuc/212:00:212
45672580,0sleep10-21swapper/109:46:481
56272570,1sleep35626-21ssh12:20:013
315452570,0sleep10-21swapper/109:27:061
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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