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2021-06-20 - 03:43

Intel(R) Core(TM) i7 CPU E 610 @ 2.53GHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #5, slot #4
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot4.osadl.org (updated Sun Jun 20, 2021 00:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
48682119100,13sleep10-21swapper/119:05:181
5573210489,11sleep30-21swapper/319:06:213
582529790,4sleep00-21swapper/019:09:350
571028174,4sleep20-21swapper/219:08:042
207372640,0sleep00-21swapper/022:46:040
585926257,2sleep20-21swapper/219:10:012
13292620,1sleep31335-21cpuspeed_turbos20:15:143
95712610,1sleep09573-21timerwakeupswit19:15:220
262722610,0sleep10-21swapper/122:10:141
611299277,18cyclictest0-21swapper/023:46:490
6112992712,14cyclictest0-21swapper/022:31:100
611299270,26cyclictest0-21swapper/000:33:280
611299269,7cyclictest0-21swapper/023:34:370
611299269,16cyclictest0-21swapper/023:14:430
611299269,16cyclictest0-21swapper/022:07:100
611299268,17cyclictest26198-21kworker/0:122:16:320
611299268,17cyclictest0-21swapper/023:55:320
611299268,17cyclictest0-21swapper/022:39:180
611299267,18cyclictest0-21swapper/023:07:320
611299267,18cyclictest0-21swapper/021:12:160
6112992612,12cyclictest0-21swapper/023:20:280
127862260,0sleep00-21swapper/022:21:070
611599250,19cyclictest0-21swapper/320:47:433
6113992523,1cyclictest0-21swapper/121:15:151
611399250,19cyclictest0-21swapper/100:33:451
611399250,19cyclictest0-21swapper/100:04:441
611299259,14cyclictest14222-21ssh22:42:190
611299258,15cyclictest0-21swapper/023:50:160
611299257,16cyclictest0-21swapper/022:53:020
611299257,16cyclictest0-21swapper/000:10:370
611299256,17cyclictest0-21swapper/023:42:410
611299256,17cyclictest0-21swapper/000:35:170
6112992512,12cyclictest0-21swapper/021:56:280
6112992510,14cyclictest2727-21ssh21:15:460
6112992510,13cyclictest3314-21ssh21:35:400
6113992422,1cyclictest0-21swapper/121:57:581
6113992415,8cyclictest0-21swapper/121:22:581
611299248,7cyclictest0-21swapper/000:23:230
611299248,15cyclictest0-21swapper/021:30:490
611299247,16cyclictest0-21swapper/022:03:050
611299246,16cyclictest26198-21kworker/0:122:57:170
611299245,17cyclictest0-21swapper/022:26:180
611299243,19cyclictest4351-21runrttasks23:27:160
611299243,19cyclictest3017-21ssh23:35:380
6112992411,12cyclictest0-21swapper/000:27:080
6112992411,12cyclictest0-21swapper/000:15:510
6112992410,13cyclictest0-21swapper/022:14:510
611299240,22cyclictest0-21swapper/023:03:350
611599230,3cyclictest0-21swapper/300:31:123
611599230,22cyclictest0-21swapper/300:20:463
611499230,4cyclictest0-21swapper/223:59:382
611499230,17cyclictest0-21swapper/223:28:162
6113992321,1cyclictest0-21swapper/121:25:581
6113992321,1cyclictest0-21swapper/119:32:111
611399230,22cyclictest0-21swapper/123:44:291
611299237,15cyclictest0-21swapper/021:40:030
6112992310,12cyclictest0-21swapper/021:28:040
6112992310,12cyclictest0-21swapper/000:09:130
611299230,10cyclictest0-21swapper/023:16:340
611299230,10cyclictest0-21swapper/021:45:210
611299230,10cyclictest0-21swapper/021:23:570
611299230,10cyclictest0-21swapper/000:01:150
611599222,19cyclictest0-21swapper/323:10:173
611599220,21cyclictest0-21swapper/323:39:013
611599220,21cyclictest0-21swapper/323:29:053
611599220,21cyclictest0-21swapper/322:30:183
611599220,20cyclictest0-21swapper/300:11:103
611599220,16cyclictest0-21swapper/319:13:573
611499225,11cyclictest0-21swapper/221:33:222
611499224,6cyclictest0-21swapper/222:45:262
611499220,4cyclictest0-21swapper/223:47:162
611499220,4cyclictest0-21swapper/222:00:482
611499220,4cyclictest0-21swapper/221:16:172
611499220,4cyclictest0-21swapper/200:15:492
611499220,3cyclictest0-21swapper/223:02:462
611499220,3cyclictest0-21swapper/222:52:372
611499220,3cyclictest0-21swapper/222:36:072
611499220,3cyclictest0-21swapper/222:20:332
611499220,3cyclictest0-21swapper/222:18:222
611499220,21cyclictest0-21swapper/223:30:402
611499220,21cyclictest0-21swapper/222:57:592
611499220,21cyclictest0-21swapper/222:26:192
611499220,21cyclictest0-21swapper/221:51:022
611499220,16cyclictest0-21swapper/200:02:302
611399222,19cyclictest0-21swapper/123:31:561
6113992220,1cyclictest0-21swapper/120:55:421
6113992220,1cyclictest0-21swapper/119:26:411
6112992214,7cyclictest0-21swapper/020:20:170
611299220,20cyclictest28719-21ssh21:51:100
153022220,1sleep20-21swapper/223:44:022
611599210,3cyclictest0-21swapper/322:24:313
611599210,3cyclictest0-21swapper/322:07:393
611599210,20cyclictest0-21swapper/323:45:053
611599210,20cyclictest0-21swapper/323:40:473
611599210,20cyclictest0-21swapper/323:21:313
611599210,20cyclictest0-21swapper/322:56:003
611599210,20cyclictest0-21swapper/322:53:013
611599210,20cyclictest0-21swapper/322:49:273
611599210,20cyclictest0-21swapper/322:26:163
611599210,20cyclictest0-21swapper/322:03:253
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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