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2022-09-25 - 14:10
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x86 Intel Core i7-E610 @2530 MHz, Linux 4.9.271-rt182 (Profile)

Latency plot of system in rack #5, slot #4
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a -t3 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot4.osadl.org (updated Sun Sep 25, 2022 00:44:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
10927213270,7sleep10-21swapper/119:07:171
10850212862,7sleep30-21swapper/319:06:183
11072212162,7sleep20-21swapper/219:09:112
109312112103,6sleep00-21swapper/019:07:200
270362680,0sleep10-21swapper/120:40:201
327392660,0sleep00-21swapper/021:11:570
313542640,1sleep30-21swapper/322:35:003
72232590,0sleep20-21swapper/220:25:192
68772580,1sleep30-21swapper/300:34:173
295132570,0sleep10-21swapper/121:26:321
113052550,0sleep00-21swapper/022:06:460
42982530,0sleep00-21swapper/000:15:240
1132399280,3cyclictest0-21swapper/221:05:122
1132399280,27cyclictest0-21swapper/221:24:262
1132399280,27cyclictest0-21swapper/220:34:252
1132399280,19cyclictest0-21swapper/220:45:132
11323992723,3cyclictest0-21swapper/223:48:102
11323992723,3cyclictest0-21swapper/221:32:532
1132399270,26cyclictest0-21swapper/222:38:332
1132399270,26cyclictest0-21swapper/222:00:172
1132399270,26cyclictest0-21swapper/221:56:172
1132399270,26cyclictest0-21swapper/221:51:132
1132399270,26cyclictest0-21swapper/221:01:272
1132399270,26cyclictest0-21swapper/220:14:422
1132399270,26cyclictest0-21swapper/200:21:232
1132399270,26cyclictest0-21swapper/200:02:102
11323992624,2cyclictest0-21swapper/222:12:572
11323992623,2cyclictest20603-21ssh00:05:412
11323992622,3cyclictest0-21swapper/223:02:572
1132399260,25cyclictest0-21swapper/223:52:312
1132399260,25cyclictest0-21swapper/223:44:582
1132399260,25cyclictest0-21swapper/223:22:552
1132399260,25cyclictest0-21swapper/223:17:252
1132399260,25cyclictest0-21swapper/220:52:312
1132399260,25cyclictest0-21swapper/220:03:032
11319992614,7cyclictest0-21swapper/100:00:171
1131999260,24cyclictest0-21swapper/122:50:291
11315992614,7cyclictest13938-21snmpd21:30:020
11323992521,3cyclictest0-21swapper/221:18:262
1132399251,2cyclictest28033-21ssh00:27:142
1132399250,24cyclictest0-21swapper/222:55:392
1132399250,24cyclictest0-21swapper/222:52:572
1132399250,24cyclictest0-21swapper/222:34:532
1132399250,24cyclictest0-21swapper/220:41:522
1132399250,24cyclictest0-21swapper/220:08:522
1132399250,24cyclictest0-21swapper/200:35:412
11319992523,1cyclictest0-21swapper/120:20:121
11319992522,2cyclictest0-21swapper/100:39:351
1131999250,24cyclictest0-21swapper/123:40:111
1131999250,19cyclictest0-21swapper/123:34:161
1131599252,22cyclictest0-21swapper/022:02:300
1131599250,24cyclictest0-21swapper/023:55:560
278442240,0sleep30-21swapper/320:15:193
11323992421,3cyclictest0-21swapper/221:43:502
1132399240,23cyclictest0-21swapper/222:41:062
1132399240,23cyclictest0-21swapper/222:20:362
1132399240,23cyclictest0-21swapper/200:18:202
1131999249,14cyclictest0-21swapper/121:50:511
1131999247,16cyclictest0-21swapper/123:11:401
1131999240,23cyclictest0-21swapper/123:01:001
1131999240,23cyclictest0-21swapper/122:12:231
1131999240,18cyclictest0-21swapper/123:24:041
1131599240,23cyclictest0-21swapper/023:07:360
1131599240,23cyclictest0-21swapper/022:51:200
1131599240,23cyclictest0-21swapper/022:34:000
1131599240,23cyclictest0-21swapper/022:14:320
1131599240,23cyclictest0-21swapper/021:52:440
11323992322,1cyclictest0-21swapper/222:17:302
1132399232,20cyclictest0-21swapper/223:38:262
1132399232,20cyclictest0-21swapper/221:47:502
11323992321,2cyclictest0-21swapper/219:31:512
11323992319,3cyclictest0-21swapper/222:25:242
11323992319,3cyclictest0-21swapper/200:32:052
1131999230,23cyclictest0-21swapper/120:33:371
1131999230,22cyclictest0-21swapper/123:57:021
1131999230,22cyclictest0-21swapper/123:48:591
1131999230,22cyclictest0-21swapper/123:17:201
1131999230,22cyclictest0-21swapper/122:46:481
1131999230,22cyclictest0-21swapper/122:07:271
1131999230,22cyclictest0-21swapper/100:22:231
1131999230,17cyclictest0-21swapper/123:38:361
1131999230,17cyclictest0-21swapper/122:19:551
1131999230,17cyclictest0-21swapper/121:57:011
1131999230,17cyclictest0-21swapper/121:14:311
1131999230,17cyclictest0-21swapper/100:11:481
1131599232,20cyclictest0-21swapper/022:56:440
1131599232,20cyclictest0-21swapper/022:21:430
1131599230,22cyclictest0-21swapper/023:46:260
1131599230,22cyclictest0-21swapper/022:35:410
1131599230,22cyclictest0-21swapper/022:29:190
1131599230,22cyclictest0-21swapper/021:43:160
1131599230,22cyclictest0-21swapper/021:28:120
1131599230,21cyclictest0-21swapper/023:27:010
1131599230,17cyclictest0-21swapper/023:35:570
1132399224,17cyclictest0-21swapper/223:25:382
11323992218,3cyclictest0-21swapper/219:25:542
1132399220,3cyclictest0-21swapper/219:42:182
1132399220,21cyclictest0-21swapper/223:34:102
1132399220,21cyclictest0-21swapper/223:11:142
1132399220,21cyclictest0-21swapper/222:05:322
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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