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2023-02-02 - 16:28

x86 Intel Core i7-E610 @2530 MHz, Linux 4.9.271-rt182 (Profile)

Latency plot of system in rack #5, slot #4
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a -t3 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot4.osadl.org (updated Thu Feb 02, 2023 12:44:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4115213674,7sleep10-21swapper/107:07:531
4116212363,8sleep20-21swapper/207:07:542
4211210899,6sleep00-21swapper/007:09:090
4003210595,7sleep30-21swapper/307:06:273
302732660,0sleep20-21swapper/209:30:192
274502650,3sleep120-21rcuc/110:30:231
263772650,0sleep20-21swapper/212:18:042
312562640,0sleep10-21swapper/111:35:001
323842630,0sleep20-21swapper/210:33:132
104592620,0sleep20-21swapper/207:40:182
234352590,0sleep123440-21kthreadcore12:00:191
168182580,0sleep10-21swapper/109:05:351
323802560,1sleep00-21swapper/009:45:280
200102540,0sleep10-21swapper/112:30:201
445499281,26cyclictest0-21swapper/208:26:072
445499280,27cyclictest0-21swapper/209:56:202
445099280,27cyclictest0-21swapper/108:51:401
445499270,26cyclictest0-21swapper/211:29:582
445499270,26cyclictest0-21swapper/210:36:482
445499270,26cyclictest0-21swapper/208:46:472
445499270,26cyclictest0-21swapper/208:35:172
445499270,26cyclictest0-21swapper/208:07:582
445499270,25cyclictest10254-21munin-plugin-st07:15:002
445099270,26cyclictest0-21swapper/108:44:471
4445992711,15cyclictest53450irq/24-enp1s010:50:120
444599270,26cyclictest0-21swapper/010:22:520
445499268,15cyclictest0-21swapper/208:40:302
445499260,26cyclictest0-21swapper/209:08:232
445499260,25cyclictest0-21swapper/211:58:452
445499260,25cyclictest0-21swapper/207:15:182
445099260,25cyclictest0-21swapper/107:45:451
445099260,25cyclictest0-21swapper/107:30:041
445099260,19cyclictest0-21swapper/111:11:251
444599260,25cyclictest0-21swapper/012:17:420
444599260,25cyclictest0-21swapper/007:25:250
445499250,24cyclictest0-21swapper/211:45:052
445499250,24cyclictest0-21swapper/209:28:362
445499250,24cyclictest0-21swapper/207:34:072
445499250,23cyclictest16576-21ssh11:41:482
445099250,24cyclictest0-21swapper/107:24:011
444599250,24cyclictest0-21swapper/011:15:480
4454992422,2cyclictest0-21swapper/211:09:202
445499241,22cyclictest0-21swapper/212:03:332
445499240,23cyclictest0-21swapper/211:03:562
445499240,19cyclictest0-21swapper/211:10:112
445099247,16cyclictest0-21swapper/109:41:231
4450992417,7cyclictest0-21swapper/107:57:221
445099240,23cyclictest0-21swapper/111:18:151
445099240,23cyclictest0-21swapper/110:17:271
445099240,23cyclictest0-21swapper/110:03:571
445099240,23cyclictest0-21swapper/107:36:421
444599247,16cyclictest0-21swapper/009:16:150
4445992416,7cyclictest0-21swapper/010:56:550
4445992416,7cyclictest0-21swapper/009:21:430
4445992415,8cyclictest0-21swapper/011:50:440
4445992415,8cyclictest0-21swapper/009:38:380
444599240,4cyclictest0-21swapper/012:36:050
444599240,23cyclictest0-21swapper/012:31:340
444599240,23cyclictest0-21swapper/011:31:370
445499232,20cyclictest0-21swapper/212:05:022
445499232,20cyclictest0-21swapper/209:23:242
4454992314,8cyclictest0-21swapper/212:37:302
445499231,21cyclictest0-21swapper/209:16:272
445499230,22cyclictest0-21swapper/209:35:322
445499230,18cyclictest0-21swapper/212:11:542
445499230,17cyclictest2518-21ssh09:46:512
445499230,17cyclictest0-21swapper/210:14:332
445099236,16cyclictest0-21swapper/111:47:211
4450992316,7cyclictest0-21swapper/109:17:531
4450992314,8cyclictest0-21swapper/109:36:271
4450992314,8cyclictest0-21swapper/109:13:071
445099231,21cyclictest0-21swapper/110:52:261
445099230,22cyclictest0-21swapper/111:27:031
445099230,22cyclictest0-21swapper/110:57:321
445099230,22cyclictest0-21swapper/110:25:141
445099230,22cyclictest0-21swapper/110:22:431
445099230,22cyclictest0-21swapper/109:59:431
445099230,22cyclictest0-21swapper/109:54:121
445099230,17cyclictest0-21swapper/112:36:191
445099230,17cyclictest0-21swapper/110:45:291
444599237,15cyclictest0-21swapper/012:20:570
444599231,16cyclictest0-21swapper/012:04:450
444599230,22cyclictest0-21swapper/012:12:490
444599230,22cyclictest0-21swapper/011:46:080
444599230,22cyclictest0-21swapper/011:42:070
444599230,22cyclictest0-21swapper/011:28:160
444599230,22cyclictest0-21swapper/011:22:320
444599230,22cyclictest0-21swapper/011:06:380
444599230,22cyclictest0-21swapper/011:02:420
444599230,22cyclictest0-21swapper/010:44:260
444599230,22cyclictest0-21swapper/010:13:260
444599230,22cyclictest0-21swapper/009:54:330
444599230,18cyclictest0-21swapper/010:16:460
444599230,17cyclictest0-21swapper/009:34:210
445499222,14cyclictest0-21swapper/211:31:412
4454992219,3cyclictest0-21swapper/207:47:102
4454992218,3cyclictest0-21swapper/207:24:342
445499221,20cyclictest0-21swapper/210:49:042
445499221,20cyclictest0-21swapper/208:32:592
445499220,22cyclictest0-21swapper/208:23:322
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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