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2024-07-27 - 08:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot4.osadl.org (updated Sat Jul 27, 2024 00:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
87852124115,6sleep10-21swapper/119:06:401
8755212462,8sleep30-21swapper/319:06:183
87422118109,6sleep00-21swapper/019:06:060
8851210996,7sleep20-21swapper/219:07:342
269342960,6sleep1922599cyclictest23:52:421
260952690,1sleep229-21rcuc/222:30:192
221442680,0sleep20-21swapper/223:36:162
291462630,1sleep08-21rcu_preempt21:10:180
59582610,0sleep00-21swapper/023:03:050
240092590,0sleep10-21swapper/122:30:181
199872590,0sleep00-21swapper/020:35:210
103322570,0sleep20-21swapper/223:31:242
29802550,0sleep10-21swapper/121:40:191
192962550,0sleep20-21swapper/223:09:132
93602530,0sleep20-21swapper/200:28:322
230592450,0sleep20-21swapper/222:43:172
922199330,25cyclictest0-21swapper/000:00:100
922199300,2cyclictest17434-21ssh22:55:120
923099271,25cyclictest0-21swapper/222:39:022
923099270,26cyclictest0-21swapper/221:32:562
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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