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2023-12-05 - 16:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot4.osadl.org (updated Tue Dec 05, 2023 12:44:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
314216696,7sleep30-21swapper/307:08:203
327012112102,7sleep10-21swapper/107:07:191
326852110101,6sleep00-21swapper/007:07:060
32642210797,7sleep20-21swapper/207:06:312
285182660,0sleep30-21swapper/310:05:273
131622630,0sleep30-21swapper/311:15:293
314202550,0sleep30-21swapper/307:30:353
277422540,0sleep30-21swapper/310:20:293
64499320,2cyclictest0-21swapper/207:40:192
303612300,0sleep1211ktimersoftd/112:11:191
64499280,27cyclictest0-21swapper/208:50:202
64099280,27cyclictest0-21swapper/107:20:251
63599280,27cyclictest0-21swapper/011:38:100
64499270,26cyclictest0-21swapper/210:19:152
64499270,26cyclictest0-21swapper/208:30:262
64499270,25cyclictest1623-21kthreadcore12:30:262
64099270,26cyclictest0-21swapper/110:42:391
64099270,26cyclictest0-21swapper/110:39:451
64099270,26cyclictest0-21swapper/110:01:511
64099270,26cyclictest0-21swapper/108:31:381
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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