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2024-06-25 - 14:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot4.osadl.org (updated Tue Jun 25, 2024 00:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
159722120110,7sleep30-21swapper/319:08:373
15933211541,7sleep10-21swapper/119:08:061
157812111101,7sleep00-21swapper/019:06:100
15753210898,7sleep20-21swapper/219:05:482
185932620,0sleep041ktimersoftd/022:15:260
81822580,0sleep00-21swapper/022:52:150
54002570,0sleep05407-21kthreadcore20:45:290
208412570,0sleep30-21swapper/320:30:223
115432560,1sleep120-21rcuc/123:35:221
180842550,0sleep218089-21kthreadcore20:30:212
65322540,0sleep00-21swapper/021:12:170
1625199270,26cyclictest0-21swapper/221:06:222
1625199270,26cyclictest0-21swapper/219:13:332
1624899270,26cyclictest0-21swapper/120:38:391
1624899270,26cyclictest0-21swapper/120:17:301
1624899270,26cyclictest0-21swapper/120:17:301
1624899270,26cyclictest0-21swapper/119:28:031
1625199260,26cyclictest0-21swapper/219:35:092
1624899260,25cyclictest12078-21ssh23:07:571
1624899260,25cyclictest0-21swapper/120:14:181
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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