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2025-05-24 - 12:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot4.osadl.org (updated Sat May 24, 2025 00:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31724210997,7sleep00-21swapper/019:09:430
31557210999,7sleep30-21swapper/319:07:323
31601210898,7sleep20-21swapper/219:08:082
31735210798,6sleep10-21swapper/119:09:521
195532730,6sleep23191799cyclictest21:40:222
34752640,0sleep30-21swapper/320:05:163
50612610,0sleep00-21swapper/023:55:190
74142570,0sleep10-21swapper/122:20:301
252532540,0sleep20-21swapper/219:25:222
139212540,0sleep10-21swapper/122:55:231
169172400,0sleep116924-21kthreadcore21:40:211
3191799290,28cyclictest0-21swapper/220:29:132
3191799281,26cyclictest0-21swapper/221:12:592
3191299280,27cyclictest0-21swapper/120:38:161
3191799270,26cyclictest0-21swapper/222:20:202
3191799270,26cyclictest0-21swapper/222:06:002
3191299270,26cyclictest0-21swapper/119:21:331
3191799260,25cyclictest0-21swapper/223:02:162
3191799260,25cyclictest0-21swapper/222:44:522
3191799260,25cyclictest0-21swapper/221:08:222
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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