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2022-05-28 - 13:16

x86 Intel Core i7-E610 @2530 MHz, Linux 4.9.271-rt182 (Profile)

Latency plot of system in rack #5, slot #4
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a -t3 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot4.osadl.org (updated Sat May 28, 2022 00:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21824210696,7sleep00-21swapper/019:05:430
2208529987,8sleep20-21swapper/219:09:072
2142029078,7sleep10-21swapper/119:05:251
2190628777,7sleep30-21swapper/319:06:473
31622690,0sleep30-21swapper/323:39:343
204412630,0sleep020446-21kthreadcore22:45:190
325942620,0sleep20-21swapper/222:35:242
167382600,0sleep20-21swapper/200:00:402
176102580,0sleep30-21swapper/322:44:223
55502560,0sleep20-21swapper/222:53:272
148972560,0sleep30-21swapper/320:20:203
279922550,0sleep10-21swapper/100:21:061
2231599315,4cyclictest0-21swapper/122:10:481
2231599300,24cyclictest0-21swapper/121:04:301
22315992912,5cyclictest0-21swapper/122:06:491
2231599290,23cyclictest0-21swapper/119:27:591
2232399280,27cyclictest0-21swapper/200:05:112
2231599282,20cyclictest0-21swapper/121:25:591
2231599280,27cyclictest0-21swapper/119:34:321
2231599280,27cyclictest0-21swapper/119:11:231
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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