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2021-09-17 - 21:49

Intel(R) Core(TM) i7 CPU E 610 @ 2.53GHz, Linux 4.16.7-rt1 (Profile)

Latency plot of system in rack #5, slot #4
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot4.osadl.org (updated Tue Jul 06, 2021 12:44:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2611629990,5sleep20-21swapper/207:07:302
2611928273,5sleep00-21swapper/007:07:310
186372750,1sleep1231ktimersoftd/112:03:521
186372750,1sleep1231ktimersoftd/112:03:521
2620127457,13sleep30-21swapper/307:08:353
225782740,0sleep20-21swapper/211:00:352
2619427257,10sleep10-21swapper/107:08:291
159142710,1sleep00-21swapper/012:01:280
159142710,1sleep00-21swapper/012:01:270
146342700,1sleep20-21swapper/209:30:182
178382690,0sleep20-21swapper/210:58:022
17592520,0sleep30-21swapper/307:25:293
186572310,0sleep018658-21ssh10:58:430
316272260,0sleep331628-21ssh11:29:083
2656799251,16cyclictest8064-21ssh11:35:102
2656799232,19cyclictest0-21swapper/210:10:172
2656699229,12cyclictest0-21swapper/109:56:481
2656699226,14cyclictest30317-21ssh12:33:321
154402220,1sleep10-21swapper/109:51:521
2656699216,2cyclictest28438-21ssh11:48:421
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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