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2023-05-30 - 20:19

x86 Intel Core i7-E610 @2530 MHz, Linux 4.9.271-rt182 (Profile)

Latency plot of system in rack #5, slot #4
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a -t3 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot4.osadl.org (updated Tue May 30, 2023 12:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31156212364,7sleep20-21swapper/207:06:232
308712121111,6sleep00-21swapper/007:05:300
313522115101,7sleep30-21swapper/307:08:563
314292113103,7sleep10-21swapper/107:09:561
180102740,0sleep30-21swapper/309:26:453
180822720,1sleep018088-21cpuspeed_turbos09:45:210
288632620,1sleep228868-21needreboot09:15:262
300792610,0sleep30-21swapper/310:05:353
129192600,0sleep20-21swapper/209:40:252
19952590,0sleep20-21swapper/209:35:302
58532570,1sleep30-21swapper/307:40:233
38662540,0sleep20-21swapper/210:40:272
178622530,0sleep30-21swapper/307:20:263
178622530,0sleep30-21swapper/307:20:253
286782420,0sleep00-21swapper/011:06:270
128142390,0sleep012820-21kthreadcore07:45:250
3161499280,27cyclictest0-21swapper/210:01:102
31612992813,13cyclictest0-21swapper/108:35:141
31612992812,15cyclictest0-21swapper/110:58:071
3161299280,27cyclictest0-21swapper/107:28:041
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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