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2023-02-06 - 14:27

x86 Intel Core i7-E610 @2530 MHz, Linux 4.9.271-rt182 (Profile)

Latency plot of system in rack #5, slot #4
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a -t3 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot4.osadl.org (updated Mon Feb 06, 2023 12:44:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12122217695,8sleep10-21swapper/107:08:271
11969215291,8sleep20-21swapper/207:06:282
2861921310,6sleep01242199cyclictest11:58:520
12208212262,6sleep30-21swapper/307:09:343
12168210797,7sleep00-21swapper/007:09:020
2394421020,0sleep023945-21ssh09:29:350
126152640,0sleep10-21swapper/111:20:321
252272600,0sleep10-21swapper/112:27:301
239952580,1sleep30-21swapper/310:08:193
186912580,0sleep30-21swapper/307:15:013
284212570,0sleep30-21swapper/307:20:263
146182560,0sleep314619-21gltestperf10:35:193
185812550,0sleep00-21swapper/007:40:170
222062530,0sleep20-21swapper/209:05:262
12428993122,3cyclictest0-21swapper/208:19:542
1242899281,25cyclictest4019-21sh09:58:582
1242899270,26cyclictest0-21swapper/210:35:562
1242899270,26cyclictest0-21swapper/209:35:432
1242899270,26cyclictest0-21swapper/207:58:302
1242899270,26cyclictest0-21swapper/207:27:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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