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2024-09-11 - 18:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack5slot4.osadl.org (updated Wed Sep 11, 2024 12:44:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11646212175,42sleep20-21swapper/207:09:072
113922113104,6sleep10-21swapper/107:05:491
116472111101,7sleep30-21swapper/307:09:083
115502109100,6sleep00-21swapper/007:07:540
234912700,0sleep30-21swapper/310:50:173
90142680,0sleep30-21swapper/309:50:203
267702650,6sleep01187699cyclictest11:40:170
311912630,0sleep10-21swapper/111:27:081
192192610,1sleep338-21rcuc/308:35:153
263412600,1sleep326349-21kthreadcore09:25:173
263412600,1sleep326349-21kthreadcore09:25:173
239932600,1sleep30-21swapper/310:32:583
148322600,2sleep229-21rcuc/210:45:192
218572570,0sleep20-21swapper/207:40:192
178662560,1sleep338-21rcuc/311:20:213
21482550,0sleep30-21swapper/312:27:463
311812440,0sleep338-21rcuc/311:43:113
1188799281,26cyclictest0-21swapper/211:39:162
1188799280,27cyclictest0-21swapper/210:43:522
1188499280,27cyclictest0-21swapper/110:54:131
1187699280,2cyclictest0-21swapper/008:15:130
1188799270,26cyclictest0-21swapper/212:07:472
1188799270,26cyclictest0-21swapper/211:54:082
1188799270,26cyclictest0-21swapper/211:32:012
1188799270,26cyclictest0-21swapper/210:06:282
1188799270,26cyclictest0-21swapper/210:04:042
1188499279,17cyclictest0-21swapper/112:01:441
1188499270,26cyclictest0-21swapper/112:37:591
1188499270,26cyclictest0-21swapper/112:26:471
1188499270,26cyclictest0-21swapper/111:50:151
1188499270,26cyclictest0-21swapper/111:35:551
1188499270,26cyclictest0-21swapper/111:05:521
1188499270,26cyclictest0-21swapper/110:58:221
1188499270,26cyclictest0-21swapper/110:34:011
1188499270,26cyclictest0-21swapper/110:07:371
1188499270,26cyclictest0-21swapper/109:51:361
1188499270,26cyclictest0-21swapper/108:48:271
1188499270,26cyclictest0-21swapper/108:25:291
1188499270,26cyclictest0-21swapper/108:21:141
1188499270,26cyclictest0-21swapper/107:46:131
1188499270,26cyclictest0-21swapper/107:34:591
1188499270,26cyclictest0-21swapper/107:16:291
1188799261,23cyclictest0-21swapper/207:30:132
1188799260,25cyclictest0-21swapper/211:11:042
1188799260,25cyclictest0-21swapper/210:33:012
1188799260,25cyclictest0-21swapper/209:22:452
1188499260,25cyclictest0-21swapper/111:19:011
1188499260,25cyclictest0-21swapper/110:28:131
1188499260,25cyclictest0-21swapper/109:57:531
1188499260,25cyclictest0-21swapper/109:44:361
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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