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2023-01-28 - 11:12

x86 Intel Core i7-E610 @2530 MHz, Linux 4.9.271-rt182 (Profile)

Latency plot of system in rack #5, slot #4
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a -t3 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack5slot4.osadl.org (updated Fri Jan 27, 2023 12:44:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1482211258,51sleep20-21swapper/207:08:392
15742111101,7sleep00-21swapper/007:09:480
13102110100,7sleep10-21swapper/107:06:241
551210795,7sleep30-21swapper/307:05:233
1617621000,5sleep0176599cyclictest10:40:150
126312730,0sleep00-21swapper/010:52:200
69272660,0sleep20-21swapper/208:30:272
173492610,0sleep10-21swapper/107:45:251
63642590,0sleep10-21swapper/108:30:221
48112590,0sleep20-21swapper/211:05:002
116842590,0sleep30-21swapper/312:37:353
98332580,0sleep00-21swapper/010:20:310
6372580,1sleep30-21swapper/311:31:323
25352580,0sleep10-21swapper/112:34:081
66322570,1sleep20-21swapper/210:05:192
309672570,0sleep30-21swapper/308:00:003
12462570,0sleep00-21swapper/011:32:070
50702560,0sleep30-21swapper/310:04:253
42432540,5sleep1176799cyclictest10:03:381
105752540,0sleep110578-21timerwakeupswit10:50:331
176799331,17cyclictest0-21swapper/108:15:161
1765993013,2cyclictest0-21swapper/011:07:190
309742290,1sleep030981-21kthreadcore09:45:220
176799280,27cyclictest0-21swapper/111:53:191
176799280,27cyclictest0-21swapper/110:42:581
177299271,2cyclictest0-21swapper/209:26:462
177299270,26cyclictest0-21swapper/210:28:592
1767992723,3cyclictest0-21swapper/110:07:331
1767992719,7cyclictest0-21swapper/107:44:341
177299260,25cyclictest0-21swapper/208:14:432
176799261,24cyclictest0-21swapper/111:56:201
176799260,25cyclictest0-21swapper/110:45:401
176799260,25cyclictest0-21swapper/108:03:401
177299250,24cyclictest0-21swapper/212:17:432
177299250,24cyclictest0-21swapper/210:24:042
1767992521,3cyclictest0-21swapper/110:58:371
1767992516,8cyclictest0-21swapper/111:26:531
176799250,24cyclictest0-21swapper/112:29:341
176799250,24cyclictest0-21swapper/112:21:161
176799250,24cyclictest0-21swapper/107:58:431
1765992521,3cyclictest0-21swapper/009:57:300
177299240,23cyclictest0-21swapper/210:11:342
177299240,23cyclictest0-21swapper/209:22:472
177299240,18cyclictest0-21swapper/211:49:402
176799240,23cyclictest0-21swapper/112:01:481
176799240,23cyclictest0-21swapper/111:43:361
176799240,23cyclictest0-21swapper/111:30:291
176799240,23cyclictest0-21swapper/109:54:131
176799240,22cyclictest0-21swapper/111:22:161
176599240,23cyclictest0-21swapper/011:45:540
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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