You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-06 - 09:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack5slot4.osadl.org (updated Fri Mar 06, 2026 00:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7469212866,8sleep30-21swapper/319:05:473
75712122112,7sleep10-21swapper/119:07:051
7655211980,9sleep20-21swapper/219:08:102
24852115105,7sleep00-21swapper/019:05:060
85192590,1sleep00-21swapper/023:25:220
796599291,27cyclictest0-21swapper/223:48:062
796599280,27cyclictest0-21swapper/219:40:152
796299280,27cyclictest0-21swapper/100:32:491
796599270,26cyclictest0-21swapper/223:50:272
796599270,26cyclictest0-21swapper/223:43:432
796599270,26cyclictest0-21swapper/223:25:332
796599270,26cyclictest0-21swapper/223:16:312
796599270,26cyclictest0-21swapper/221:55:232
796599270,26cyclictest0-21swapper/220:53:592
7962992622,3cyclictest0-21swapper/123:02:461
7962992622,3cyclictest0-21swapper/122:13:211
7962992618,7cyclictest0-21swapper/120:08:521
796299260,25cyclictest0-21swapper/123:46:271
796299260,25cyclictest0-21swapper/123:08:511
796299260,25cyclictest0-21swapper/122:47:151
796299260,25cyclictest0-21swapper/121:37:111
796299260,25cyclictest0-21swapper/121:12:291
796299260,25cyclictest0-21swapper/120:17:251
796299260,25cyclictest0-21swapper/119:29:061
7965992521,3cyclictest0-21swapper/221:05:172
796299250,24cyclictest0-21swapper/122:06:531
796299250,24cyclictest0-21swapper/121:57:561
796299250,24cyclictest0-21swapper/121:33:081
796299250,24cyclictest0-21swapper/121:06:501
796599249,14cyclictest0-21swapper/200:30:132
7965992422,2cyclictest0-21swapper/219:32:222
7965992420,3cyclictest0-21swapper/221:17:562
7962992422,2cyclictest0-21swapper/123:34:361
7962992422,2cyclictest0-21swapper/122:55:421
7962992422,2cyclictest0-21swapper/121:02:021
7962992422,2cyclictest0-21swapper/100:09:551
7965992320,2cyclictest0-21swapper/220:03:162
7962992322,1cyclictest0-21swapper/119:42:401
7962992321,2cyclictest0-21swapper/120:53:021
7962992321,2cyclictest0-21swapper/120:49:141
7962992320,3cyclictest0-21swapper/100:24:531
796299230,22cyclictest0-21swapper/123:51:451
7965992220,2cyclictest0-21swapper/222:20:532
7965992220,2cyclictest0-21swapper/219:26:002
7965992219,2cyclictest0-21swapper/220:09:212
7965992214,7cyclictest0-21swapper/223:34:162
796599221,20cyclictest0-21swapper/222:25:032
796599221,20cyclictest0-21swapper/221:42:142
7962992221,1cyclictest0-21swapper/120:11:191
7962992221,1cyclictest0-21swapper/100:35:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional