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2022-06-29 - 15:08

x86 Intel Core i7-E610 @2530 MHz, Linux 4.9.271-rt182 (Profile)

Latency plot of system in rack #5, slot #4
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a -t3 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack5slot4.osadl.org (updated Wed Jun 29, 2022 12:44:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2830213660,8sleep10-21swapper/107:05:391
2995210796,7sleep20-21swapper/207:07:492
3162210596,6sleep00-21swapper/007:09:550
3018121000,2sleep30-21swapper/307:05:123
102472670,0sleep20-21swapper/210:07:062
84962630,0sleep30-21swapper/311:42:413
185262600,1sleep018531-21kthreadcore07:45:190
88572590,1sleep30-21swapper/309:20:093
315562580,0sleep010-21rcuc/009:15:140
131752580,1sleep10-21swapper/109:53:191
195202550,0sleep00-21swapper/011:00:250
119062550,0sleep30-21swapper/309:51:583
56772530,0sleep20-21swapper/211:40:192
33912530,0sleep20-21swapper/211:25:172
281882530,0sleep00-21swapper/009:29:190
335099280,27cyclictest0-21swapper/207:55:192
335099270,26cyclictest0-21swapper/208:35:462
335099270,26cyclictest0-21swapper/207:38:372
334699270,26cyclictest0-21swapper/111:12:091
334699270,26cyclictest0-21swapper/111:05:521
334699270,26cyclictest0-21swapper/109:11:011
334699270,26cyclictest0-21swapper/108:16:591
334699270,26cyclictest0-21swapper/108:09:221
334299270,26cyclictest0-21swapper/011:56:100
334299270,26cyclictest0-21swapper/011:32:120
334299270,26cyclictest0-21swapper/011:27:580
334299270,26cyclictest0-21swapper/011:24:180
334299270,26cyclictest0-21swapper/010:07:350
335099260,25cyclictest0-21swapper/209:44:502
334699260,25cyclictest0-21swapper/112:31:341
334699260,25cyclictest0-21swapper/109:41:231
334699260,25cyclictest0-21swapper/109:03:461
334699260,25cyclictest0-21swapper/108:43:111
334699260,25cyclictest0-21swapper/108:34:291
334699260,25cyclictest0-21swapper/107:52:191
334699260,25cyclictest0-21swapper/107:38:221
334699260,25cyclictest0-21swapper/107:29:131
334299260,25cyclictest0-21swapper/010:20:150
334299260,25cyclictest0-21swapper/009:56:150
269652260,0sleep20-21swapper/211:20:172
335099250,19cyclictest5787-21ssh12:30:162
3346992518,7cyclictest0-21swapper/108:26:171
334699250,24cyclictest0-21swapper/111:34:141
334699250,24cyclictest0-21swapper/109:36:061
334699250,24cyclictest0-21swapper/108:12:241
334699250,24cyclictest0-21swapper/107:49:331
334699250,24cyclictest0-21swapper/107:24:271
3342992516,8cyclictest0-21swapper/011:09:030
334299250,24cyclictest0-21swapper/012:27:450
334299250,24cyclictest0-21swapper/009:48:060
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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