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2025-07-03 - 06:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack5slot4.osadl.org (updated Thu Jul 03, 2025 00:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
25137212462,6sleep10-21swapper/119:09:251
24989211962,54sleep20-21swapper/219:07:302
251392111102,6sleep30-21swapper/319:09:273
251262109100,6sleep00-21swapper/019:09:150
308892700,0sleep30-21swapper/321:22:313
126012650,0sleep30-21swapper/321:15:023
319682620,0sleep00-21swapper/020:40:130
44972540,0sleep30-21swapper/322:41:373
248322510,0sleep30-21swapper/322:35:293
251742500,0sleep325180-21kthreadcore20:05:213
251742500,0sleep325180-21kthreadcore20:05:203
311492420,0sleep231148-21ssh23:57:082
2535799280,27cyclictest0-21swapper/219:15:082
2535499280,27cyclictest0-21swapper/123:05:341
2535499280,27cyclictest0-21swapper/120:46:451
2535499270,26cyclictest0-21swapper/122:54:251
2535499270,26cyclictest0-21swapper/122:04:301
2535499270,26cyclictest0-21swapper/121:01:031
2535499270,26cyclictest0-21swapper/120:40:561
2535499270,26cyclictest0-21swapper/120:26:201
2535499270,26cyclictest0-21swapper/120:19:531
2535499270,26cyclictest0-21swapper/119:28:231
2535499270,26cyclictest0-21swapper/119:22:521
2535499270,26cyclictest0-21swapper/119:11:101
2535499270,26cyclictest0-21swapper/100:29:391
2534699270,26cyclictest0-21swapper/021:10:520
262452260,3sleep010-21rcuc/019:10:150
2535799260,25cyclictest0-21swapper/221:24:572
2535799260,25cyclictest0-21swapper/219:54:032
2535799260,24cyclictest25288-21ssh23:24:112
2535499260,25cyclictest0-21swapper/123:25:341
2535499260,25cyclictest0-21swapper/123:11:111
2535499260,25cyclictest0-21swapper/121:54:311
2535499260,25cyclictest0-21swapper/120:56:141
2535499260,25cyclictest0-21swapper/120:37:421
2535499260,25cyclictest0-21swapper/120:34:531
2535499260,25cyclictest0-21swapper/120:23:361
2535499260,25cyclictest0-21swapper/119:50:141
2535499260,25cyclictest0-21swapper/100:05:331
2534699260,25cyclictest0-21swapper/022:16:010
2535799250,24cyclictest0-21swapper/222:43:132
2535499250,24cyclictest0-21swapper/123:36:591
2535499250,24cyclictest0-21swapper/121:06:081
25346992516,8cyclictest0-21swapper/023:32:580
25346992515,9cyclictest19764-21ssh22:35:170
2534699250,24cyclictest0-21swapper/022:04:540
2535799240,23cyclictest0-21swapper/222:14:552
2535799240,23cyclictest0-21swapper/221:42:312
2535499242,21cyclictest0-21swapper/122:49:131
2535499240,23cyclictest0-21swapper/122:22:231
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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