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2021-01-20 - 14:12

Intel(R) Core(TM) i7 CPU E 610 @ 2.53GHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #5, slot #4
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack5slot4.osadl.org (updated Wed Jan 20, 2021 12:44:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1405828274,4sleep30-21swapper/307:05:413
1348827666,5sleep20-21swapper/207:05:132
1427727559,12sleep10-21swapper/107:08:321
1423927557,15sleep00-21swapper/007:08:030
1463499280,17cyclictest0-21swapper/212:30:032
14633992715,11cyclictest0-21swapper/109:55:041
1463399260,20cyclictest0-21swapper/111:18:231
14633992220,1cyclictest0-21swapper/110:32:091
14635992119,1cyclictest0-21swapper/311:52:383
1463399217,13cyclictest0-21swapper/112:25:151
1463399217,13cyclictest0-21swapper/112:25:151
14633992119,1cyclictest0-21swapper/111:32:541
1463399210,20cyclictest0-21swapper/110:14:231
1463399210,20cyclictest0-21swapper/108:10:371
1463399210,20cyclictest0-21swapper/107:45:361
14632992118,2cyclictest3257-21snmpd10:52:230
14632992118,2cyclictest3257-21snmpd10:29:090
14632992118,2cyclictest3257-21snmpd10:03:080
14632992118,2cyclictest3257-21snmpd09:33:370
14632992118,2cyclictest3257-21snmpd09:08:530
14632992118,2cyclictest3257-21snmpd09:08:530
14632992118,2cyclictest3257-21snmpd08:20:360
14632992118,2cyclictest3257-21snmpd08:07:510
1463599206,8cyclictest777-21ntp_states10:50:113
14635992018,1cyclictest0-21swapper/309:30:083
1463599200,1cyclictest0-21swapper/311:00:543
1463599200,19cyclictest0-21swapper/312:33:103
1463599200,19cyclictest0-21swapper/312:20:073
1463599200,19cyclictest0-21swapper/312:00:393
1463599200,19cyclictest0-21swapper/309:20:373
1463599200,19cyclictest0-21swapper/308:55:583
1463599200,19cyclictest0-21swapper/308:24:063
1463599200,19cyclictest0-21swapper/307:51:363
1463599200,14cyclictest0-21swapper/312:18:283
14634992018,1cyclictest3257-21snmpd12:35:252
14634992018,1cyclictest3257-21snmpd12:19:392
14634992017,2cyclictest0-21swapper/210:23:052
1463499200,14cyclictest0-21swapper/211:38:082
14633992018,1cyclictest0-21swapper/112:31:381
14633992018,1cyclictest0-21swapper/111:08:081
14633992018,1cyclictest0-21swapper/108:21:361
14633992017,2cyclictest0-21swapper/112:20:391
14633992017,2cyclictest0-21swapper/111:52:241
14633992017,2cyclictest0-21swapper/108:45:371
14633992017,2cyclictest0-21swapper/108:15:511
1463399200,2cyclictest0-21swapper/108:36:521
1463399200,2cyclictest0-21swapper/108:08:221
1463399200,1cyclictest0-21swapper/110:37:241
1463399200,1cyclictest0-21swapper/109:23:081
1463399200,19cyclictest0-21swapper/109:42:371
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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