You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2023-06-05 - 22:12

x86 Intel Core i7-E610 @2530 MHz, Linux 4.9.271-rt182 (Profile)

Latency plot of system in rack #5, slot #4
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a -t3 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack5slot4.osadl.org (updated Mon Jun 05, 2023 12:44:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31662211660,6sleep10-21swapper/107:06:541
316092116106,7sleep30-21swapper/307:06:123
318692113102,6sleep00-21swapper/007:09:350
31715211275,8sleep20-21swapper/207:07:362
163192750,5sleep23207899cyclictest11:30:272
94042620,0sleep10-21swapper/110:24:441
144622620,0sleep10-21swapper/107:45:271
229682610,0sleep10-21swapper/112:39:351
140272600,0sleep314032-21kthreadcore10:10:283
318842590,0sleep00-21swapper/010:20:150
244012570,1sleep30-21swapper/307:25:303
158262570,0sleep20-21swapper/209:56:052
48852540,0sleep00-21swapper/010:35:290
222192530,0sleep00-21swapper/010:15:260
146922530,0sleep30-21swapper/312:00:403
3207899280,27cyclictest0-21swapper/211:22:472
3207899270,26cyclictest0-21swapper/211:26:322
3207899259,15cyclictest0-21swapper/207:10:262
3207899250,24cyclictest0-21swapper/212:09:312
32075992518,7cyclictest0-21swapper/109:08:571
32075992518,7cyclictest0-21swapper/109:08:571
32075992518,7cyclictest0-21swapper/107:11:261
3207899244,19cyclictest0-21swapper/210:05:182
3207899240,23cyclictest0-21swapper/208:05:182
3207599240,23cyclictest0-21swapper/110:15:521
32070992415,8cyclictest0-21swapper/011:03:130
3207099240,23cyclictest0-21swapper/011:08:460
3207099240,18cyclictest0-21swapper/009:30:540
32078992321,2cyclictest0-21swapper/210:24:312
32078992316,6cyclictest0-21swapper/209:20:472
32078992315,7cyclictest0-21swapper/210:31:252
3207899231,21cyclictest0-21swapper/211:03:242
3207899231,21cyclictest0-21swapper/210:03:432
3207899230,22cyclictest0-21swapper/210:14:102
3207899230,17cyclictest0-21swapper/210:57:192
32075992320,3cyclictest0-21swapper/110:26:131
32075992317,6cyclictest0-21swapper/112:05:561
32075992316,7cyclictest0-21swapper/111:33:581
32075992314,8cyclictest0-21swapper/109:13:211
3207599231,3cyclictest0-21swapper/110:40:411
3207599231,21cyclictest0-21swapper/108:27:201
3207599230,22cyclictest0-21swapper/111:20:291
3207599230,22cyclictest0-21swapper/111:12:071
3207599230,22cyclictest0-21swapper/111:01:201
3207599230,22cyclictest0-21swapper/110:57:421
3207599230,22cyclictest0-21swapper/110:32:101
3207599230,22cyclictest0-21swapper/110:14:011
3207599230,22cyclictest0-21swapper/109:38:481
3207599230,22cyclictest0-21swapper/109:24:051
3207099232,15cyclictest0-21swapper/010:53:350
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional