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2023-12-11 - 03:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Mon Dec 11, 2023 01:01:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3700599198190,6cyclictest0-21swapper/3000:12:5324
3700599198190,6cyclictest0-21swapper/3000:12:5224
369849919157,116cyclictest0-21swapper/1219:10:244
369849919157,116cyclictest0-21swapper/1219:10:244
3697199191173,16cyclictest0-21swapper/323:45:1423
3697199191173,16cyclictest0-21swapper/323:45:1423
3700499190167,12cyclictest0-21swapper/2920:20:4222
3700499190167,12cyclictest0-21swapper/2920:20:4222
3697099190156,32cyclictest0-21swapper/221:21:5612
3697099190156,32cyclictest0-21swapper/221:21:5612
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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