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2023-02-06 - 23:39

x86 Intel Xeon E5-2650Lv2 @1700 MHz, Linux 4.18.7-rt5 (Profile)

Latency plot of system in rack #6, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Up99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat Feb 04, 2023 03:01:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
34126992601,255cyclictest37561-21sshd23:20:3127
34126992601,255cyclictest37561-21sshd23:20:3027
34126992601,255cyclictest37561-21sshd23:20:3027
3413799249242,4cyclictest0-21swapper/3900:25:3833
3413799249242,4cyclictest0-21swapper/3900:25:3833
3412099244240,1cyclictest0-21swapper/3119:15:1525
3412099244240,1cyclictest0-21swapper/3119:15:1425
3413799228225,1cyclictest0-21swapper/3919:15:1533
3413799228225,1cyclictest0-21swapper/3919:15:1533
3412699228221,3cyclictest25029-21CPU27
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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