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2024-05-29 - 01:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Tue May 28, 2024 13:01:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3671799229208,12cyclictest33590-21inotify_reader07:25:1712
3671799229208,12cyclictest33590-21inotify_reader07:25:1712
3676199210119,85cyclictest4907-21CPU33
3676199210119,85cyclictest4907-21CPU33
3676199210119,85cyclictest4907-21CPU33
3676199191148,27cyclictest0-21swapper/3912:03:5133
3676199191148,27cyclictest0-21swapper/3912:03:5133
3673699191185,4cyclictest0-21swapper/1811:23:3510
3673699191185,4cyclictest0-21swapper/1811:23:3510
3673699191185,4cyclictest0-21swapper/1811:23:3510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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