You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-03-25 - 03:27
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Tue Mar 25, 2025 01:00:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17910993133,290cyclictest9327-21CPU36
17910993133,290cyclictest9327-21CPU36
179109924412,214cyclictest34994-21inotify_reader22:35:2136
179109924412,214cyclictest34994-21inotify_reader22:35:2136
179109924112,225cyclictest0-21swapper/620:32:2736
1792899239218,7cyclictest0-21swapper/2021:47:5913
1792899239218,7cyclictest0-21swapper/2021:47:5913
17910992382,5cyclictest4635-21CPU36
17910992382,5cyclictest4635-21CPU36
17910992382,5cyclictest4635-21CPU36
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional