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2024-04-25 - 22:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Thu Apr 25, 2024 13:01:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3278599219187,28cyclictest0-21swapper/212:37:3612
3278599219187,28cyclictest0-21swapper/212:37:3612
3278599219187,28cyclictest0-21swapper/212:37:3612
3281099205191,12cyclictest1992-21nfsd10:34:5120
3281099205191,12cyclictest1992-21nfsd10:34:5120
3281799204192,10cyclictest0-21swapper/3411:22:5528
3281799204192,10cyclictest0-21swapper/3411:22:5528
3281799204192,10cyclictest0-21swapper/3411:22:5528
3281799199178,11cyclictest0-21swapper/3410:06:1028
3281799199178,11cyclictest0-21swapper/3410:06:1028
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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