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2025-07-09 - 11:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Wed Jul 09, 2025 01:01:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2769399249211,19cyclictest31372-21TaskSchedulerSi20:40:2131
2769399249211,19cyclictest31372-21TaskSchedulerSi20:40:2131
2769399225203,12cyclictest26635-21NetworkChangeNo00:35:2031
2769399225203,12cyclictest26635-21NetworkChangeNo00:35:2031
2769399225203,12cyclictest26635-21NetworkChangeNo00:35:2031
2762899224199,7cyclictest0-21swapper/423:41:4834
2762899224199,7cyclictest0-21swapper/423:41:4834
27682992144,84cyclictest10092-21inotify_reader19:45:2226
2769399210203,5cyclictest0-21swapper/3723:15:2031
2769399210203,5cyclictest0-21swapper/3723:15:2031
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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