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2022-12-01 - 23:58

x86 Intel Xeon E5-2650Lv2 @1700 MHz, Linux 4.18.7-rt5 (Profile)

Latency plot of system in rack #6, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Up99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100, highest latencies:
System rack6slot0.osadl.org (updated Thu Oct 27, 2022 14:46:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2686299272241,20cyclictest37732-21sh09:50:4331
2686299272241,20cyclictest37732-21sh09:50:4331
2686299259237,16cyclictest0-21swapper/3711:25:2731
2686299259237,16cyclictest0-21swapper/3711:25:2731
2686299259237,16cyclictest0-21swapper/3711:25:2631
2686299258244,10cyclictest14500-21run-parts11:43:4631
2686299258244,10cyclictest14500-21run-parts11:43:4531
2686299250238,6cyclictest0-21swapper/3711:34:2731
2686299250238,6cyclictest0-21swapper/3711:34:2731
2686299248231,11cyclictest32141-21systemd-cgroups10:45:3731
2686299248231,11cyclictest32141-21systemd-cgroups10:45:3631
2686299243229,8cyclictest19426-21CPU31
2686299243229,8cyclictest19426-21CPU31
2686299243225,10cyclictest138450irq/36-eno1-TxR10:33:5331
2686299243225,10cyclictest138450irq/36-eno1-TxR10:33:5331
2686299242229,9cyclictest19425-21CPU31
2686299242229,9cyclictest19425-21CPU31
2686299241229,7cyclictest1354-21ModemManager10:53:3231
2686299241229,7cyclictest1354-21ModemManager10:53:3231
2686299241229,7cyclictest0-21swapper/3710:10:1131
2686299241229,7cyclictest0-21swapper/3710:10:1031
2686299241226,11cyclictest0-21swapper/3710:00:2731
2686299241226,11cyclictest0-21swapper/3710:00:2731
2686299240231,6cyclictest12253-21sshd10:40:4431
2686299240231,6cyclictest12253-21sshd10:40:4331
2686299240230,7cyclictest35767-21sshd11:12:1131
2686299240230,7cyclictest35767-21sshd11:12:1131
2686299240226,8cyclictest19429-21CPU31
2686299240226,8cyclictest19429-21CPU31
2686299238230,6cyclictest31956-21sshd10:26:1231
2686299238230,6cyclictest31956-21sshd10:26:1131
2686299237224,8cyclictest19428-21CPU31
2686299237224,8cyclictest19428-21CPU31
2686299236225,7cyclictest0-21swapper/3712:20:0131
2686299236225,7cyclictest0-21swapper/3712:20:0031
2686299235228,4cyclictest10482-21sshd12:32:2531
2686299235228,4cyclictest10482-21sshd12:32:2531
2686299235226,6cyclictest5963-21latency_hist07:35:0331
2686299235226,6cyclictest5963-21latency_hist07:35:0231
2686299235226,6cyclictest12682-21gdbus11:45:0931
2686299235226,6cyclictest12682-21gdbus11:45:0831
2686299235226,6cyclictest0-21swapper/3712:03:3531
2686299235226,6cyclictest0-21swapper/3712:03:3531
2686299235225,7cyclictest4292-21qemu-system-x8609:46:3131
2686299235225,7cyclictest4292-21qemu-system-x8609:46:3031
2686299235225,7cyclictest0-21swapper/3710:55:4231
2686299235225,7cyclictest0-21swapper/3710:55:4131
2686299235225,6cyclictest0-21swapper/3709:30:3331
2686299235225,6cyclictest0-21swapper/3709:30:3331
2686299234225,6cyclictest0-21swapper/3712:07:2331
2686299234225,6cyclictest0-21swapper/3712:07:2331
2686299234224,7cyclictest0-21swapper/3709:28:5331
2686299234224,7cyclictest0-21swapper/3709:28:5231
2686299234220,11cyclictest0-21swapper/3710:07:3131
2686299234220,11cyclictest0-21swapper/3710:07:3131
2686299234220,11cyclictest0-21swapper/3710:07:3131
2686299234220,10cyclictest0-21swapper/3709:11:2431
2686299234220,10cyclictest0-21swapper/3709:11:2431
2686299233225,6cyclictest0-21swapper/3710:36:4131
2686299233225,6cyclictest0-21swapper/3710:36:4031
2686299233224,4cyclictest19426-21CPU31
2686299233224,4cyclictest19426-21CPU31
2686299232221,6cyclictest4296-21CPU31
2686299232221,6cyclictest4296-21CPU31
2686299231224,5cyclictest0-21swapper/3712:25:2131
2686299231224,5cyclictest0-21swapper/3712:25:2131
2686299231224,5cyclictest0-21swapper/3707:50:2731
2686299231224,5cyclictest0-21swapper/3707:50:2631
2686299231222,6cyclictest12649-21sshd09:15:5231
2686299231222,6cyclictest12649-21sshd09:15:5131
2686299231222,5cyclictest0-21swapper/3708:32:5931
2686299231222,5cyclictest0-21swapper/3708:32:5931
2686299231220,6cyclictest19430-21CPU31
2686299231220,6cyclictest19430-21CPU31
2686299231218,8cyclictest26418-21gdbus11:16:2431
2686299231218,8cyclictest26418-21gdbus11:16:2431
2686299230223,5cyclictest0-21swapper/3711:04:2731
2686299230223,5cyclictest0-21swapper/3711:04:2731
2686299230222,5cyclictest0-21swapper/3711:35:5431
2686299230222,5cyclictest0-21swapper/3711:35:5331
2686299230221,6cyclictest0-21swapper/3710:20:0531
2686299230221,6cyclictest0-21swapper/3710:20:0531
2686299230220,6cyclictest0-21swapper/3712:20:4831
2686299230220,6cyclictest0-21swapper/3712:20:4831
2686299230213,11cyclictest0-21swapper/3711:50:2031
2686299230213,11cyclictest0-21swapper/3711:50:1931
2686299229214,9cyclictest0-21swapper/3710:23:2431
2686299229214,9cyclictest0-21swapper/3710:23:2331
2686299229213,9cyclictest0-21swapper/3711:09:5031
2686299229213,9cyclictest0-21swapper/3711:09:4931
2686299229213,9cyclictest0-21swapper/3711:09:4931
2686299228221,3cyclictest19424-21CPU31
2686299228221,3cyclictest19424-21CPU31
2686299228220,4cyclictest19430-21CPU31
2686299228220,4cyclictest19430-21CPU31
2686299228218,6cyclictest4296-21CPU31
2686299228218,6cyclictest4296-21CPU31
2686299227221,4cyclictest0-21swapper/3708:55:0331
2686299227221,4cyclictest0-21swapper/3708:55:0231
2686299227217,7cyclictest0-21swapper/3708:05:2331
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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